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Tue, 27 Jan 2026 10:55:11 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v11 6/8] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters Date: Tue, 27 Jan 2026 10:54:58 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002320:EE_|DS0PR12MB7928:EE_ X-MS-Office365-Filtering-Correlation-Id: fc668462-5c19-49e9-3b39-08de5dd5a5c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ejiJyYBsk4FTBIcb4ZepxKJ6GIJRiBymFoHVHyeiDt7PT+6w3AHgZKrY5WBe?= =?us-ascii?Q?8dRnJEPUO6KzdZd+SYRR/7khQZhOBHx9bJIpdPgTZv8dtaaP2bUb0rKKz6Mf?= =?us-ascii?Q?INgfoEOWOdF1S3JFP9jEb2KScSrpHKWVzY9gzdCS5RaV+6D27uinZkqDXVEa?= =?us-ascii?Q?+mlJayO+acBfFlsbQGSDQa60M2e5Vl2LDOTUftQjUiYpp3UJpjAH/yp22E2X?= =?us-ascii?Q?mZ4PzVSomitx0QSXHogAHAtj4vEKBNwHJBXLqxg020WfISUiVZKnCeBYO+Kc?= =?us-ascii?Q?W9nNbtyh6Vy850mAQ0olUdWsxK1PFm5G8dhRfpLUDdkMcBebv8urUWYcKdq4?= =?us-ascii?Q?rp64ZbuwTLxIHCRCO5Dq8jF7porK/b+KL2ihCXyK9CEtnaY5wBIRprI4Dl7Z?= =?us-ascii?Q?ZT3DC0WW7L6MbJNWpdD6KBNKfVIxAvZ4bl8rcweeBBWOMqSAGQVgRqiI/F/h?= =?us-ascii?Q?VCkxXDavV5erTGh7/QFGFB4zNUm7OWfz70baQXN/LC5u2Z2uCNL3vrVLxZJb?= =?us-ascii?Q?/j+mVloOgGyHIC5NouY8LAjQTeV9GTd5ZGlL31WjRSU6LPRIsxKF+RAh8Mcg?= =?us-ascii?Q?uo7zHcsh63OPcxi7AVUZbXO3y9yeSacFEk5IVf4OUVu3yH839WwHswY62E12?= =?us-ascii?Q?vnfYpxJpb0N+ZLzcSmanIDAJNg02cfgM/tihRf58gCQV52SHjmkueALdU00j?= =?us-ascii?Q?hjBpGQiAQuwrzBm5S9J90FlNhV5l/Gu46nNdAWdR93rznR9YlcSZ0btzCf1u?= =?us-ascii?Q?MG47Ku5gILu3ciP+4bwQeEgVKzsQDYpWNUnKrrNd/ajfj6lt3BspErQFLSgz?= =?us-ascii?Q?FpVbPDtUoaRWAH47yLVAgfuZFKS0isKDR1F5YjcHLzq9g680b/DEhlajyfwa?= =?us-ascii?Q?hasWtYAZxKD+cuaEMhCgD54ObdW2CG1f2XyweVIdmnRogC9udWuzVfMk2ef0?= =?us-ascii?Q?tTeKrWbOfawQSa1RY7/z+fTkULZfQ7usbA9G2FkDN4HVDQLi91vTS891OWdT?= =?us-ascii?Q?1CbNtd7u4x8faHmQx7DGgtsKHIrzf2VqSRkUw6h+43hmEsTFQKi6XfnQ6TH9?= =?us-ascii?Q?FjLZimgCsx6lBTY3CiDY4EupY/n+6FX6+BRy4oPsqkQ2Sa/FdwQGJ6KZ2WNW?= =?us-ascii?Q?AwsORj01/brtIhd0RNviCRhQlHZpIiFBB+OT3eFA5lDW5RpGzkLhooAn2Xpz?= =?us-ascii?Q?1JV30lJKKoas0WbjG7DhUYQme79Rl4PnNXs4C21I7ZEJUoxSMewklNR/1THV?= =?us-ascii?Q?z7rZy13ITDWBNABtq6UhcJ6SNHbaM2dsxkWr6ZoC0zSQLYQOu2gaS+U1kVKA?= =?us-ascii?Q?203G12bmm1Jsi9XfLNdFB5kC+RAk5tEddxf7YVmBMMUN71Pbd+898gsdNjxh?= =?us-ascii?Q?PWtubdGkZUFMYIGit6aiYp8Dr0MHHxZOiyaVVzVRTDIgJZbrmBC3Vr9t+wt5?= =?us-ascii?Q?2lX2Iu3zCwYeoM6VnQlWwBbugbytmNNc2u7sgMAm/ftrKZlPH4sjRVEflUxv?= =?us-ascii?Q?kC4wCcj6fYg4S5BAHr8z/EEpjQ87CQ6Q+QcJaWCHONk/sLUff1RunsdSZbi+?= =?us-ascii?Q?nZnlXhU0Ew2szWOFbaInHNoR+ckkEypzl70YlBTHXSA7QWGMqT5mY0cKYUAb?= =?us-ascii?Q?EWZgV+icJ+wMZwKpXMxSGJrurrkHHyceg/NKHKbsjvbfa/kLAoDOXp+xVqC0?= =?us-ascii?Q?sT7FVQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 18:55:32.3520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc668462-5c19-49e9-3b39-08de5dd5a5c6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7928 Content-Type: text/plain; charset="utf-8" Update the invs array with the invalidations required by each domain type during attachment operations. Only an SVA domain or a paging domain will have an invs array: a. SVA domain will add an INV_TYPE_S1_ASID per SMMU and an INV_TYPE_ATS per SID b. Non-nesting-parent paging domain with no ATS-enabled master will add a single INV_TYPE_S1_ASID or INV_TYPE_S2_VMID per SMMU c. Non-nesting-parent paging domain with ATS-enabled master(s) will do (b) and add an INV_TYPE_ATS per SID d. Nesting-parent paging domain will add an INV_TYPE_S2_VMID followed by an INV_TYPE_S2_VMID_S1_CLEAR per vSMMU. For an ATS-enabled master, it will add an INV_TYPE_ATS_FULL per SID Note that case #d prepares for a future implementation of VMID allocation which requires a followup series for S2 domain sharing. So when a nesting parent domain is attached through a vSMMU instance using a nested domain. VMID will be allocated per vSMMU instance v.s. currectly per S2 domain. The per-domain invalidation is not needed until the domain is attached to a master (when it starts to possibly use TLB). This will make it possible to attach the domain to multiple SMMUs and avoid unnecessary invalidation overhead during teardown if no STEs/CDs refer to the domain. It also means that when the last device is detached, the old domain must flush its ASID or VMID, since any new iommu_unmap() call would not trigger invalidations given an empty domain->invs array. Introduce some arm_smmu_invs helper functions for building scratch arrays, preparing and installing old/new domain's invalidation arrays. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 17 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 262 +++++++++++++++++++- 2 files changed, 278 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5e0e5055af1e..83d7e4952dff 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1102,6 +1102,21 @@ static inline bool arm_smmu_master_canwbs(struct arm= _smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } =20 +/** + * struct arm_smmu_inv_state - Per-domain invalidation array state + * @invs_ptr: points to the domain->invs (unwinding nesting/etc.) or is NU= LL if + * no change should be made + * @old_invs: the original invs array + * @new_invs: for new domain, this is the new invs array to update domain-= >invs; + * for old domain, this is the master->build_invs to pass in as= the + * to_unref argument to an arm_smmu_invs_unref() call + */ +struct arm_smmu_inv_state { + struct arm_smmu_invs __rcu **invs_ptr; + struct arm_smmu_invs *old_invs; + struct arm_smmu_invs *new_invs; +}; + struct arm_smmu_attach_state { /* Inputs */ struct iommu_domain *old_domain; @@ -1111,6 +1126,8 @@ struct arm_smmu_attach_state { ioasid_t ssid; /* Resulting state */ struct arm_smmu_vmaster *vmaster; + struct arm_smmu_inv_state old_domain_invst; + struct arm_smmu_inv_state new_domain_invst; bool ats_enabled; }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5a0a8b136352..2114af1dd5ed 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3143,6 +3143,121 @@ static void arm_smmu_disable_iopf(struct arm_smmu_m= aster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +static struct arm_smmu_inv * +arm_smmu_master_build_inv(struct arm_smmu_master *master, + enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, + size_t pgsize) +{ + struct arm_smmu_invs *build_invs =3D master->build_invs; + struct arm_smmu_inv *cur, inv =3D { + .smmu =3D master->smmu, + .type =3D type, + .id =3D id, + .pgsize =3D pgsize, + }; + + if (WARN_ON(build_invs->num_invs >=3D build_invs->max_invs)) + return NULL; + cur =3D &build_invs->inv[build_invs->num_invs]; + build_invs->num_invs++; + + *cur =3D inv; + switch (type) { + case INV_TYPE_S1_ASID: + /* + * For S1 page tables the driver always uses VMID=3D0, and the + * invalidation logic for this type will set it as well. + */ + if (master->smmu->features & ARM_SMMU_FEAT_E2H) { + cur->size_opcode =3D CMDQ_OP_TLBI_EL2_VA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_EL2_ASID; + } else { + cur->size_opcode =3D CMDQ_OP_TLBI_NH_VA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_NH_ASID; + } + break; + case INV_TYPE_S2_VMID: + cur->size_opcode =3D CMDQ_OP_TLBI_S2_IPA; + cur->nsize_opcode =3D CMDQ_OP_TLBI_S12_VMALL; + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + cur->size_opcode =3D cur->nsize_opcode =3D CMDQ_OP_TLBI_NH_ALL; + break; + case INV_TYPE_ATS: + case INV_TYPE_ATS_FULL: + cur->size_opcode =3D cur->nsize_opcode =3D CMDQ_OP_ATC_INV; + cur->ssid =3D ssid; + break; + } + + return cur; +} + +/* + * Use the preallocated scratch array at master->build_invs, to build a to= _merge + * or to_unref array, to pass into a following arm_smmu_invs_merge/unref()= call. + * + * Do not free the returned invs array. It is reused, and will be overwrit= ten by + * the next arm_smmu_master_build_invs() call. + */ +static struct arm_smmu_invs * +arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enable= d, + ioasid_t ssid, struct arm_smmu_domain *smmu_domain) +{ + const bool nesting =3D smmu_domain->nest_parent; + size_t pgsize =3D 0, i; + + iommu_group_mutex_assert(master->dev); + + master->build_invs->num_invs =3D 0; + + /* Range-based invalidation requires the leaf pgsize for calculation */ + if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) + pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, + smmu_domain->cd.asid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + case ARM_SMMU_DOMAIN_S2: + if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, + smmu_domain->s2_cfg.vmid, + IOMMU_NO_PASID, pgsize)) + return NULL; + break; + default: + WARN_ON(true); + return NULL; + } + + /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ + if (nesting) { + if (!arm_smmu_master_build_inv( + master, INV_TYPE_S2_VMID_S1_CLEAR, + smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + return NULL; + } + + for (i =3D 0; ats_enabled && i < master->num_streams; i++) { + /* + * If an S2 used as a nesting parent is changed we have no + * option but to completely flush the ATC. + */ + if (!arm_smmu_master_build_inv( + master, nesting ? INV_TYPE_ATS_FULL : INV_TYPE_ATS, + master->streams[i].id, ssid, 0)) + return NULL; + } + + /* Note this build_invs must have been sorted */ + + return master->build_invs; +} + static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, struct iommu_domain *domain, ioasid_t ssid) @@ -3172,6 +3287,135 @@ static void arm_smmu_remove_master_domain(struct ar= m_smmu_master *master, kfree(master_domain); } =20 +/* + * During attachment, the updates of the two domain->invs arrays are seque= nced: + * 1. new domain updates its invs array, merging master->build_invs + * 2. new domain starts to include the master during its invalidation + * 3. master updates its STE switching from the old domain to the new dom= ain + * 4. old domain still includes the master during its invalidation + * 5. old domain updates its invs array, unreferencing master->build_invs + * + * For 1 and 5, prepare the two updated arrays in advance, handling any ch= anges + * that can possibly failure. So the actual update of either 1 or 5 won't = fail. + * arm_smmu_asid_lock ensures that the old invs in the domains are intact = while + * we are sequencing to update them. + */ +static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *stat= e, + struct iommu_domain *new_domain) +{ + struct arm_smmu_domain *old_smmu_domain =3D + to_smmu_domain_devices(state->old_domain); + struct arm_smmu_domain *new_smmu_domain =3D + to_smmu_domain_devices(new_domain); + struct arm_smmu_master *master =3D state->master; + ioasid_t ssid =3D state->ssid; + + /* + * At this point a NULL domain indicates the domain doesn't use the + * IOTLB, see to_smmu_domain_devices(). + */ + if (new_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + struct arm_smmu_invs *build_invs; + + invst->invs_ptr =3D &new_smmu_domain->invs; + invst->old_invs =3D rcu_dereference_protected( + new_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + build_invs =3D arm_smmu_master_build_invs( + master, state->ats_enabled, ssid, new_smmu_domain); + if (!build_invs) + return -EINVAL; + + invst->new_invs =3D + arm_smmu_invs_merge(invst->old_invs, build_invs); + if (IS_ERR(invst->new_invs)) + return PTR_ERR(invst->new_invs); + } + + if (old_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + + invst->invs_ptr =3D &old_smmu_domain->invs; + /* A re-attach case might have a different ats_enabled state */ + if (new_smmu_domain =3D=3D old_smmu_domain) + invst->old_invs =3D state->new_domain_invst.new_invs; + else + invst->old_invs =3D rcu_dereference_protected( + old_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + /* For old_smmu_domain, new_invs points to master->build_invs */ + invst->new_invs =3D arm_smmu_master_build_invs( + master, master->ats_enabled, ssid, old_smmu_domain); + } + + return 0; +} + +/* Must be installed before arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + + if (!invst->invs_ptr) + return; + + rcu_assign_pointer(*invst->invs_ptr, invst->new_invs); + kfree_rcu(invst->old_invs, rcu); +} + +static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv) +{ + struct arm_smmu_cmdq_ent cmd =3D {}; + + switch (inv->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid =3D inv->id; + break; + case INV_TYPE_S2_VMID: + /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ + cmd.tlbi.vmid =3D inv->id; + break; + default: + return; + } + + cmd.opcode =3D inv->nsize_opcode; + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); +} + +/* Should be installed after arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + struct arm_smmu_invs *old_invs =3D invst->old_invs; + struct arm_smmu_invs *new_invs; + + lockdep_assert_held(&arm_smmu_asid_lock); + + if (!invst->invs_ptr) + return; + + arm_smmu_invs_unref(old_invs, invst->new_invs); + /* + * When an IOTLB tag (the first entry in invs->new_invs) is no longer use= d, + * it means the ASID or VMID will no longer be invalidated by map/unmap a= nd + * must be cleaned right now. The rule is that any ASID/VMID not in an in= vs + * array must be left cleared in the IOTLB. + */ + if (!READ_ONCE(invst->new_invs->inv[0].users)) + arm_smmu_inv_flush_iotlb_tag(&invst->new_invs->inv[0]); + + new_invs =3D arm_smmu_invs_purge(old_invs); + if (!new_invs) + return; + + rcu_assign_pointer(*invst->invs_ptr, new_invs); + kfree_rcu(old_invs, rcu); +} + /* * Start the sequence to attach a domain to a master. The sequence contain= s three * steps: @@ -3229,12 +3473,16 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_= state *state, arm_smmu_ats_supported(master); } =20 + ret =3D arm_smmu_attach_prepare_invs(state, new_domain); + if (ret) + return ret; + if (smmu_domain) { if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { ret =3D arm_smmu_attach_prepare_vmaster( state, to_smmu_nested_domain(new_domain)); if (ret) - return ret; + goto err_unprepare_invs; } =20 master_domain =3D kzalloc(sizeof(*master_domain), GFP_KERNEL); @@ -3282,6 +3530,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_install_new_domain_invs(state); } =20 if (!state->ats_enabled && master->ats_enabled) { @@ -3301,6 +3551,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, kfree(master_domain); err_free_vmaster: kfree(state->vmaster); +err_unprepare_invs: + kfree(state->new_domain_invst.new_invs); return ret; } =20 @@ -3332,6 +3584,7 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_st= ate *state) } =20 arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); + arm_smmu_install_old_domain_invs(state); master->ats_enabled =3D state->ats_enabled; } =20 @@ -3513,12 +3766,19 @@ static int arm_smmu_blocking_set_dev_pasid(struct i= ommu_domain *new_domain, { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(old_domain); struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + struct arm_smmu_attach_state state =3D { + .master =3D master, + .old_domain =3D old_domain, + .ssid =3D pasid, + }; =20 mutex_lock(&arm_smmu_asid_lock); + arm_smmu_attach_prepare_invs(&state, NULL); arm_smmu_clear_cd(master, pasid); if (master->ats_enabled) arm_smmu_atc_inv_master(master, pasid); arm_smmu_remove_master_domain(master, &smmu_domain->domain, pasid); + arm_smmu_install_old_domain_invs(&state); mutex_unlock(&arm_smmu_asid_lock); =20 /* --=20 2.43.0