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Thu, 19 Mar 2026 12:52:09 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , Subject: [PATCH v4 06/10] iommu/arm-smmu-v3: Introduce INV_TYPE_S2_VMID_VSMMU Date: Thu, 19 Mar 2026 12:51:52 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000015:EE_|BN7PPF9E4583E15:EE_ X-MS-Office365-Filtering-Correlation-Id: 121df83f-ba63-4c32-6b36-08de85f10d56 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|56012099003|18002099003|22082099003|3613699012; X-Microsoft-Antispam-Message-Info: vkEM5kqtJ/3jXH9p1OJvlrflqOmO8gD91fukWX2FRA1VJwjrBQX33IcIDsdKKv+1Hzk62GO9ox//k0OU8RZ/aJcvD6TFFJSn4QKQq82F8aUndXXpMCay/TkiOrZ588OZk8owp8/32/FWWfrhIKraKUQkcrJD6OzkvpfgP8GObNjhnzB2ivyvs0aWKKdaKc9ee3VxKOnq1Y/CbJn9miSQ6KRHriTcFd4WFpaJImiYBCo5aK06jXX50guDuRFhpZwr/QqpWp9GoX+0JCvdC1AuVw/GAxDBKW3XxYpHYWoExUBX/ev1gEqkHvuA1SzllFVV42mordQZyL9shXQ/MOR48ptvfI5HB9iDWAxaTDXNIukPe4zI17hcYjzpd8INxGlkYB+VsjQ474NY0Zn2zRc9mABLX6DKNYI3FOQVQxKQr0c2VlMjsch3KAVKQiSxiAoX/QNTM8rEpPhsjVA7I89js9qIa9R1YDJGa6Bfds/MS1F6la2UZ3Jfw7+deOvvv62EDHv51UqKgMn0so1U/HJGxIVlm6UUAoKolRL6VuTk3gj41K7AjpaZvoUP6/VV2z2iDdb5ZNRmE00U7ePyKUJrWxDl4Pcr71aBgqkonR6Bs07mCTwoUAIBBU+WLSPNi8Z2Vktwknsu/IHf6byLzo1/Eu883FbeAQePdWNwcfgDk1ax8+nCqWQIfzSSmLtYMG8CrA74I8OZ0lpzlmhXEL1qwunY2m0J05fLPnjIjMCB0F1ezV6aPQA5x2knjljZS81C1d+MZ49vreg0YLCkpwtY9aAXSKvVYrZ/bEIboQCLoLiF0MfYsEeIfpTDEo1GdC0fteFXsDNNrtXy5I37CotDDw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(56012099003)(18002099003)(22082099003)(3613699012);DIR:OUT;SFP:1101; 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charset="utf-8" A VMID held by a vSMMU is required to setup hardware (e.g. tegra241-cmdqv) during its initialization. So, it should be allocated in the ->viommu_init callback. This makes the VMID lifecycle unique than a VMID allocated for a naked S2 attachment. Introduce an INV_TYPE_S2_VMID_VSMMU to prepare for this case. In arm_smmu_alloc_iotlb_tag(), retrieve the preallocated VMID on the vSMMU directly instead of allocating a new one. In arm_smmu_find_iotlb_tag(), continue searching in the smmu_domain->invs, using the type INV_TYPE_S2_VMID_VSMMU. This means a second device attached to a nested domain associated with the same vSMMU instance shall reuse the VMID held by the vSMMU. (FWIW, device attached to a nesting parent domain will have an INV_TYPE_S2_VMID and will not resue the VMID on any vSMMU.) Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 +++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 +++++++++++++++--- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 385dc76bc1b9f..c722df9b21982 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -655,6 +655,7 @@ struct arm_smmu_cmdq_batch { enum arm_smmu_inv_type { INV_TYPE_S1_ASID, INV_TYPE_S2_VMID, + INV_TYPE_S2_VMID_VSMMU, INV_TYPE_S2_VMID_S1_CLEAR, INV_TYPE_ATS, INV_TYPE_ATS_FULL, @@ -676,7 +677,9 @@ struct arm_smmu_inv { =20 static inline void arm_smmu_inv_assert_iotlb_tag(struct arm_smmu_inv *inv) { - WARN_ON(inv->type !=3D INV_TYPE_S1_ASID && inv->type !=3D INV_TYPE_S2_VMI= D); + WARN_ON(inv->type !=3D INV_TYPE_S1_ASID && + inv->type !=3D INV_TYPE_S2_VMID && + inv->type !=3D INV_TYPE_S2_VMID_VSMMU); } =20 static inline bool arm_smmu_inv_is_ats(const struct arm_smmu_inv *inv) @@ -1195,6 +1198,13 @@ struct arm_vsmmu { u16 vmid; }; =20 +static inline struct arm_vsmmu *to_vsmmu(struct iommu_domain *domain) +{ + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) + return to_smmu_nested_domain(domain)->vsmmu; + return NULL; +} + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, enum iommu_hw_info_type *type); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ca7628abef5bd..130b6442af37f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1987,7 +1987,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 - WARN_ON(tag->type !=3D INV_TYPE_S2_VMID); + WARN_ON(tag->type !=3D INV_TYPE_S2_VMID && + tag->type !=3D INV_TYPE_S2_VMID_VSMMU); =20 memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( @@ -2683,6 +2684,7 @@ static void __arm_smmu_domain_inv_range(struct arm_sm= mu_invs *invs, granule); break; case INV_TYPE_S2_VMID: + case INV_TYPE_S2_VMID_VSMMU: cmd.tlbi.vmid =3D cur->id; cmd.tlbi.leaf =3D leaf; arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, @@ -3246,7 +3248,10 @@ int arm_smmu_find_iotlb_tag(struct iommu_domain *dom= ain, tag->type =3D INV_TYPE_S1_ASID; break; case ARM_SMMU_DOMAIN_S2: - tag->type =3D INV_TYPE_S2_VMID; + if (to_vsmmu(domain)) + tag->type =3D INV_TYPE_S2_VMID_VSMMU; + else + tag->type =3D INV_TYPE_S2_VMID; break; default: return -EINVAL; @@ -3270,6 +3275,12 @@ static int arm_smmu_alloc_iotlb_tag(struct iommu_dom= ain *domain, if (!ret || ret !=3D -ENOENT) return ret; =20 + if (tag->type =3D=3D INV_TYPE_S2_VMID_VSMMU) { + /* Use the pre-allocated VMID from vSMMU */ + tag->id =3D to_vsmmu(domain)->vmid; + return 0; + } + /* FIXME replace with an actual allocation from the bitmap */ if (tag->type =3D=3D INV_TYPE_S1_ASID) tag->id =3D smmu_domain->cd.asid; @@ -3313,6 +3324,7 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, } break; case INV_TYPE_S2_VMID: + case INV_TYPE_S2_VMID_VSMMU: cur->size_opcode =3D CMDQ_OP_TLBI_S2_IPA; cur->nsize_opcode =3D CMDQ_OP_TLBI_S12_VMALL; break; @@ -3357,7 +3369,7 @@ arm_smmu_master_build_invs(struct arm_smmu_master *ma= ster, bool ats_enabled, return NULL; =20 /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ - if (nesting) { + if (tag->type =3D=3D INV_TYPE_S2_VMID_VSMMU) { if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID_S1_CLEAR, tag->id, IOMMU_NO_PASID, 0)) --=20 2.43.0