From nobody Sat Feb 7 08:13:49 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB1201EA7CB; Sun, 26 Oct 2025 23:45:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761522353; cv=none; b=XL7nbINgsKaU1gICIJpSZ4nbXApkUW89GSc4n4bCC5FQu7zYN5xZ5N43GByFGjEBd9lgmniASKSqV2DRjoDCdwiB3ReGXTUCq7vEkPDmQWtGvt3rfJu7XMjVL7Ez5sc6t6jOFpYYi/bkeAuTDkPbdSX7Vj+TkM8J7TVs4SvFZ2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761522353; c=relaxed/simple; bh=5kXC1CAWgnUKu6BSqlCTKpFKsw7PdJ3JVTfJU0qHLss=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=fD1Ht1jdV0OndeQYgRTUHdvLh8FK2Na8hP6zgYfDIDymqyxvAF2sEQF8+sjwIj808IKGAldZFoyPGL8XNEMe00/gKAvk+W765vjrMs1J/9EPWNLTN+pbL7gkXtOMZoTpMXgd66tAVXv9t5ne/KQm+35jG6P5xiWrd1EoIy0WUsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1vDAQk-000000007eS-1CkN; Sun, 26 Oct 2025 23:45:46 +0000 Date: Sun, 26 Oct 2025 23:45:42 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v3 07/12] net: dsa: lantiq_gswip: allow adjusting MII delays Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently the MII clk vs. data delay is configured based on the PHY interface mode. In addition to that add support for setting up MII delays using the standard Device Tree properties 'tx-internal-delay-ps' and 'rx-internal-delay-ps' and only fall back to using the PHY interface mode in case both properties are unused. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.h | 4 +++ drivers/net/dsa/lantiq/lantiq_gswip_common.c | 31 ++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index 42000954d842..0c32ec85e127 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -82,6 +82,10 @@ #define GSWIP_MII_PCDU5 0x05 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) +#define GSWIP_MII_PCDU_TXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PC= DU_TXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY(x) u16_encode_bits(((x) / 500), GSWIP_MII_PC= DU_RXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY_DEFAULT 2000 /* picoseconds */ +#define GSWIP_MII_PCDU_TXDLY_DEFAULT 2000 /* picoseconds */ =20 /* GSWIP Core Registers */ #define GSWIP_SWRES 0x000 diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa= /lantiq/lantiq_gswip_common.c index 94b187899db6..60a83093cd10 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c @@ -622,6 +622,34 @@ static int gswip_port_vlan_filtering(struct dsa_switch= *ds, int port, return 0; } =20 +static bool gswip_mii_delay_setup(struct gswip_priv *priv, struct dsa_port= *dp) +{ + u32 tx_delay =3D GSWIP_MII_PCDU_TXDLY_DEFAULT; + u32 rx_delay =3D GSWIP_MII_PCDU_RXDLY_DEFAULT; + struct device_node *port_dn =3D dp->dn; + bool used; + int ret; + + ret =3D of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); + if (ret && ret !=3D -EINVAL) + return ret; + used =3D !ret; + + ret =3D of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); + if (ret && ret !=3D -EINVAL) + return ret; + used |=3D !ret; + + if (used) + gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | + GSWIP_MII_PCDU_RXDLY_MASK, + GSWIP_MII_PCDU_TXDLY(tx_delay) | + GSWIP_MII_PCDU_RXDLY(rx_delay), + dp->index); + + return used; +} + static int gswip_setup(struct dsa_switch *ds) { unsigned int cpu_ports =3D dsa_cpu_ports(ds); @@ -1419,6 +1447,9 @@ static void gswip_phylink_mac_config(struct phylink_c= onfig *config, GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, miicfg, port); =20 + if (gswip_mii_delay_setup(priv, dp)) + return; + switch (state->interface) { case PHY_INTERFACE_MODE_RGMII_ID: gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | --=20 2.51.1