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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH net-next v5 1/2] dt-bindings: net: pse-pd: Add bindings for Si3474 PSE controller Thread-Topic: [PATCH net-next v5 1/2] dt-bindings: net: pse-pd: Add bindings for Si3474 PSE controller Thread-Index: AQHb8lZqngBpGj//mUCerkRi/bElpg== Date: Fri, 11 Jul 2025 11:24:50 +0000 Message-ID: <580972fd-56e9-4f7a-bedf-6dde54f54add@adtran.com> References: In-Reply-To: Accept-Language: pl-PL, en-US Content-Language: pl-PL X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=adtran.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BE1PPF3198F3A62:EE_|BE0P281MB0050:EE_ x-ms-office365-filtering-correlation-id: 77ab8e59-663a-4901-0f6d-08ddc06d8cb6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|921020|38070700018; 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charset="utf-8" Content-ID: Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: adtran.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BE1PPF3198F3A62.DEUP281.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 77ab8e59-663a-4901-0f6d-08ddc06d8cb6 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2025 11:24:50.0633 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 423946e4-28c0-4deb-904c-a4a4b174fb3f X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: whjp++ZfNwsv/FyaeyHODSTPOYgArO3M3rBtHtFtlWQIWhleBnvxC4lHzSrLBO8v9Cbbn28nrn5PM4OuJgBdAA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BE0P281MB0050 From: Piotr Kubik Add the Si3474 I2C Power Sourcing Equipment controller device tree bindings documentation. Signed-off-by: Piotr Kubik Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kory Maincent --- .../bindings/net/pse-pd/skyworks,si3474.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pse-pd/skyworks,s= i3474.yaml diff --git a/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.y= aml b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml new file mode 100644 index 000000000000..edd36a43a387 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/skyworks,si3474.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Skyworks Si3474 Power Sourcing Equipment controller + +maintainers: + - Piotr Kubik + +allOf: + - $ref: pse-controller.yaml# + +properties: + compatible: + enum: + - skyworks,si3474 + + reg: + maxItems: 2 + + reg-names: + items: + - const: main + - const: secondary + + channels: + description: The Si3474 is a single-chip PoE PSE controller managing + 8 physical power delivery channels. Internally, it's structured + into two logical "Quads". + Quad 0 Manages physical channels ('ports' in datasheet) 0, 1, 2, 3 + Quad 1 Manages physical channels ('ports' in datasheet) 4, 5, 6, 7. + + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^channel@[0-7]$': + type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - pse-pis + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-pse@26 { + compatible =3D "skyworks,si3474"; + reg-names =3D "main", "secondary"; + reg =3D <0x26>, <0x27>; + + channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + phys0_0: channel@0 { + reg =3D <0>; + }; + phys0_1: channel@1 { + reg =3D <1>; + }; + phys0_2: channel@2 { + reg =3D <2>; + }; + phys0_3: channel@3 { + reg =3D <3>; + }; + phys0_4: channel@4 { + reg =3D <4>; + }; + phys0_5: channel@5 { + reg =3D <5>; + }; + phys0_6: channel@6 { + reg =3D <6>; + }; + phys0_7: channel@7 { + reg =3D <7>; + }; + }; + pse-pis { + #address-cells =3D <1>; + #size-cells =3D <0>; + pse_pi0: pse-pi@0 { + reg =3D <0>; + #pse-cells =3D <0>; + pairset-names =3D "alternative-a", "alternative-b"; + pairsets =3D <&phys0_0>, <&phys0_1>; + polarity-supported =3D "MDI-X", "S"; + vpwr-supply =3D <®_pse>; + }; + pse_pi1: pse-pi@1 { + reg =3D <1>; + #pse-cells =3D <0>; + pairset-names =3D "alternative-a", "alternative-b"; + pairsets =3D <&phys0_2>, <&phys0_3>; + polarity-supported =3D "MDI-X", "S"; + vpwr-supply =3D <®_pse>; + }; + pse_pi2: pse-pi@2 { + reg =3D <2>; + #pse-cells =3D <0>; + pairset-names =3D "alternative-a", "alternative-b"; + pairsets =3D <&phys0_4>, <&phys0_5>; + polarity-supported =3D "MDI-X", "S"; + vpwr-supply =3D <®_pse>; + }; + pse_pi3: pse-pi@3 { + reg =3D <3>; + #pse-cells =3D <0>; + pairset-names =3D "alternative-a", "alternative-b"; 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charset="utf-8" Content-ID: Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: adtran.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BE1PPF3198F3A62.DEUP281.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 592baa82-c160-4c42-b102-08ddc06d941b X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2025 11:25:02.5131 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 423946e4-28c0-4deb-904c-a4a4b174fb3f X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RZBaa6lvUz3U7/TGTtD8vF9FiWoZjNURyjatZH6lC1AkgZBWJEW4po0oNId3yhYdym9gjCdJF9INes65/TAPJg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BE0P281MB0050 From: Piotr Kubik Add a driver for the Skyworks Si3474 I2C Power Sourcing Equipment controller. Driver supports basic features of Si3474 IC: - get port status, - get port power, - get port voltage, - enable/disable port power. Only 4p configurations are supported at this moment. Signed-off-by: Piotr Kubik --- drivers/net/pse-pd/Kconfig | 11 + drivers/net/pse-pd/Makefile | 1 + drivers/net/pse-pd/si3474.c | 584 ++++++++++++++++++++++++++++++++++++ 3 files changed, 596 insertions(+) create mode 100644 drivers/net/pse-pd/si3474.c diff --git a/drivers/net/pse-pd/Kconfig b/drivers/net/pse-pd/Kconfig index 7fab916a7f46..7ef29657ee5d 100644 --- a/drivers/net/pse-pd/Kconfig +++ b/drivers/net/pse-pd/Kconfig @@ -32,6 +32,17 @@ config PSE_PD692X0 To compile this driver as a module, choose M here: the module will be called pd692x0. =20 +config PSE_SI3474 + tristate "Si3474 PSE controller" + depends on I2C + help + This module provides support for Si3474 regulator based Ethernet + Power Sourcing Equipment. + Only 4-pair PSE configurations are supported. + + To compile this driver as a module, choose M here: the + module will be called si3474. + config PSE_TPS23881 tristate "TPS23881 PSE controller" depends on I2C diff --git a/drivers/net/pse-pd/Makefile b/drivers/net/pse-pd/Makefile index 9d2898b36737..cc78f7ea7f5f 100644 --- a/drivers/net/pse-pd/Makefile +++ b/drivers/net/pse-pd/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PSE_CONTROLLER) +=3D pse_core.o =20 obj-$(CONFIG_PSE_REGULATOR) +=3D pse_regulator.o obj-$(CONFIG_PSE_PD692X0) +=3D pd692x0.o +obj-$(CONFIG_PSE_SI3474) +=3D si3474.o obj-$(CONFIG_PSE_TPS23881) +=3D tps23881.o diff --git a/drivers/net/pse-pd/si3474.c b/drivers/net/pse-pd/si3474.c new file mode 100644 index 000000000000..ade0c4eabf5c --- /dev/null +++ b/drivers/net/pse-pd/si3474.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the Skyworks Si3474 PoE PSE Controller + * + * Chip Architecture & Terminology: + * + * The Si3474 is a single-chip PoE PSE controller managing 8 physical power + * delivery channels. Internally, it's structured into two logical "Quads". + * + * Quad 0: Manages physical channels ('ports' in datasheet) 0, 1, 2, 3 + * Quad 1: Manages physical channels ('ports' in datasheet) 4, 5, 6, 7 + * + * Each Quad is accessed via a separate I2C address. The base address rang= e is + * set by hardware pins A1-A4, and the specific address selects Quad 0 (us= ually + * the lower/even address) or Quad 1 (usually the higher/odd address). + * See datasheet Table 2.2 for the address mapping. + * + * While the Quads manage channel-specific operations, the Si3474 package = has + * several resources shared across the entire chip: + * - Single RESETb input pin. + * - Single INTb output pin (signals interrupts from *either* Quad). + * - Single OSS input pin (Emergency Shutdown). + * - Global I2C Address (0x7F) used for firmware updates. + * - Global status monitoring (Temperature, VDD/VPWR Undervoltage Lockout). + * + * Driver Architecture: + * + * To handle the mix of per-Quad access and shared resources correctly, th= is + * driver treats the entire Si3474 package as one logical device. The driv= er + * instance associated with the primary I2C address (Quad 0) takes ownersh= ip. + * It discovers and manages the I2C client for the secondary address (Quad= 1). + * This primary instance handles shared resources like IRQ management and + * registers a single PSE controller device representing all logical PIs. + * Internal functions route I2C commands to the appropriate Quad's i2c_cli= ent + * based on the target channel or PI. + * + * Terminology Mapping: + * + * - "PI" (Power Interface): Refers to the logical PSE port as defined by + * IEEE 802.3 (typically corresponds to an RJ45 connector). This is the + * `id` (0-7) used in the pse_controller_ops. + * - "Channel": Refers to one of the 8 physical power control paths within + * the Si3474 chip itself (hardware channels 0-7). This terminology is + * used internally within the driver to avoid confusion with 'ports'. + * - "Quad": One of the two internal 4-channel management units within the + * Si3474, each accessed via its own I2C address. + * + * Relationship: + * - A 2-Pair PoE PI uses 1 Channel. + * - A 4-Pair PoE PI uses 2 Channels. + * + * ASCII Schematic: + * + * +-----------------------------------------------------+ + * | Si3474 Chip | + * | | + * | +---------------------+ +---------------------+ | + * | | Quad 0 | | Quad 1 | | + * | | Channels 0, 1, 2, 3 | | Channels 4, 5, 6, 7 | | + * | +----------^----------+ +-------^-------------+ | + * | I2C Addr 0 | | I2C Addr 1 | + * | +------------------------+ | + * | (Primary Driver Instance) (Managed by Primary) | + * | | + * | Shared Resources (affect whole chip): | + * | - Single INTb Output -> Handled by Primary | + * | - Single RESETb Input | + * | - Single OSS Input -> Handled by Primary | + * | - Global I2C Addr (0x7F) for Firmware Update | + * | - Global Status (Temp, VDD/VPWR UVLO) | + * +-----------------------------------------------------+ + * | | | | | | | | + * Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 (Physical Channels) + * + * Example Mapping (Logical PI to Physical Channel(s)): + * * 2-Pair Mode (8 PIs): + * PI 0 -> Ch 0 + * PI 1 -> Ch 1 + * ... + * PI 7 -> Ch 7 + * * 4-Pair Mode (4 PIs): + * PI 0 -> Ch 0 + Ch 1 (Managed via Quad 0 Addr) + * PI 1 -> Ch 2 + Ch 3 (Managed via Quad 0 Addr) + * PI 2 -> Ch 4 + Ch 5 (Managed via Quad 1 Addr) + * PI 3 -> Ch 6 + Ch 7 (Managed via Quad 1 Addr) + * (Note: Actual mapping depends on Device Tree and PORT_REMAP config) + */ + +#include +#include +#include +#include +#include + +#define SI3474_MAX_CHANS 8 + +#define MANUFACTURER_ID 0x08 +#define IC_ID 0x05 +#define SI3474_DEVICE_ID (MANUFACTURER_ID << 3 | IC_ID) + +/* Misc registers */ +#define VENDOR_IC_ID_REG 0x1B +#define TEMPERATURE_REG 0x2C +#define FIRMWARE_REVISION_REG 0x41 +#define CHIP_REVISION_REG 0x43 + +/* Main status registers */ +#define POWER_STATUS_REG 0x10 +#define PORT_MODE_REG 0x12 +#define DETECT_CLASS_ENABLE_REG 0x14 + +/* PORTn Current */ +#define PORT1_CURRENT_LSB_REG 0x30 + +/* PORTn Current [mA], return in [nA] */ +/* 1000 * ((PORTn_CURRENT_MSB << 8) + PORTn_CURRENT_LSB) / 16384 */ +#define SI3474_NA_STEP (1000 * 1000 * 1000 / 16384) + +/* VPWR Voltage */ +#define VPWR_LSB_REG 0x2E +#define VPWR_MSB_REG 0x2F + +/* PORTn Voltage */ +#define PORT1_VOLTAGE_LSB_REG 0x32 + +/* VPWR Voltage [V], return in [uV] */ +/* 60 * (( VPWR_MSB << 8) + VPWR_LSB) / 16384 */ +#define SI3474_UV_STEP (1000 * 1000 * 60 / 16384) + +/* Helper macros */ +#define CHAN_IDX(chan) ((chan) % 4) +#define CHAN_BIT(chan) BIT(CHAN_IDX(chan)) +#define CHAN_UPPER_BIT(chan) BIT(CHAN_IDX(chan) + 4) + +#define CHAN_MASK(chan) (0x03U << (2 * CHAN_IDX(chan))) +#define CHAN_REG(base, chan) ((base) + (CHAN_IDX(chan) * 4)) + +struct si3474_pi_desc { + u8 chan[2]; + bool is_4p; +}; + +struct si3474_priv { + struct i2c_client *client[2]; + struct pse_controller_dev pcdev; + struct device_node *np; + struct si3474_pi_desc pi[SI3474_MAX_CHANS]; +}; + +static struct si3474_priv *to_si3474_priv(struct pse_controller_dev *pcdev) +{ + return container_of(pcdev, struct si3474_priv, pcdev); +} + +static void si3474_get_channels(struct si3474_priv *priv, int id, + u8 *chan0, u8 *chan1) +{ + *chan0 =3D priv->pi[id].chan[0]; + *chan1 =3D priv->pi[id].chan[1]; +} + +static struct i2c_client *si3474_get_chan_client(struct si3474_priv *priv, + u8 chan) +{ + return (chan < 4) ? priv->client[0] : priv->client[1]; +} + +static int si3474_pi_get_admin_state(struct pse_controller_dev *pcdev, int= id, + struct pse_admin_state *admin_state) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + s32 ret; + u8 chan0, chan1; + bool is_enabled =3D false; + + if (id >=3D SI3474_MAX_CHANS) + return -ERANGE; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) { + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN; + return ret; + } + + is_enabled =3D (ret & CHAN_MASK(chan0)) | + (ret & CHAN_MASK(chan1)); + + if (is_enabled) + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; + else + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; + + return 0; +} + +static int si3474_pi_get_pw_status(struct pse_controller_dev *pcdev, int i= d, + struct pse_pw_status *pw_status) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + s32 ret; + u8 chan0, chan1; + bool delivering =3D false; + + if (id >=3D SI3474_MAX_CHANS) + return -ERANGE; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + ret =3D i2c_smbus_read_byte_data(client, POWER_STATUS_REG); + if (ret < 0) { + pw_status->c33_pw_status =3D ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN; + return ret; + } + + delivering =3D ret & (CHAN_UPPER_BIT(chan0) | CHAN_UPPER_BIT(chan1)); + + if (delivering) + pw_status->c33_pw_status =3D + ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; + else + pw_status->c33_pw_status =3D ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; + + return 0; +} + +static int si3474_get_of_channels(struct si3474_priv *priv) +{ + struct pse_pi *pi; + u32 chan_id; + s32 ret; + u8 pi_no; + + for (pi_no =3D 0; pi_no < SI3474_MAX_CHANS; pi_no++) { + pi =3D &priv->pcdev.pi[pi_no]; + u8 pairset_no; + + for (pairset_no =3D 0; pairset_no < 2; pairset_no++) { + if (!pi->pairset[pairset_no].np) + continue; + + ret =3D of_property_read_u32(pi->pairset[pairset_no].np, + "reg", &chan_id); + if (ret) { + dev_err(&priv->client[0]->dev, + "Failed to read channel reg property\n"); + return ret; + } + if (chan_id > SI3474_MAX_CHANS) { + dev_err(&priv->client[0]->dev, + "Incorrect channel number: %d\n", chan_id); + return ret; + } + + priv->pi[pi_no].chan[pairset_no] =3D chan_id; + /* Mark as 4-pair if second pairset is present */ + priv->pi[pi_no].is_4p =3D (pairset_no =3D=3D 1); + } + } + + return 0; +} + +static int si3474_setup_pi_matrix(struct pse_controller_dev *pcdev) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + s32 ret; + + ret =3D si3474_get_of_channels(priv); + if (ret < 0) { + dev_warn(&priv->client[0]->dev, + "Unable to parse DT PSE power interface matrix\n"); + } + return ret; +} + +static int si3474_pi_enable(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + s32 ret; + u8 chan0, chan1; + u8 val =3D 0; + + if (id >=3D SI3474_MAX_CHANS) + return -ERANGE; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Release PI from shutdown */ + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) + return ret; + + val =3D (u8)ret; + val |=3D CHAN_MASK(chan0); + val |=3D CHAN_MASK(chan1); + + ret =3D i2c_smbus_write_byte_data(client, PORT_MODE_REG, val); + if (ret) + return ret; + + /* DETECT_CLASS_ENABLE must be set when using AUTO mode, + * otherwise PI does not power up - datasheet section 2.10.2 + */ + val =3D CHAN_BIT(chan0) | CHAN_UPPER_BIT(chan0) | + CHAN_BIT(chan1) | CHAN_UPPER_BIT(chan1); + + ret =3D i2c_smbus_write_byte_data(client, DETECT_CLASS_ENABLE_REG, val); + if (ret) + return ret; + + return 0; +} + +static int si3474_pi_disable(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + s32 ret; + u8 chan0, chan1; + u8 val =3D 0; + + if (id >=3D SI3474_MAX_CHANS) + return -ERANGE; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Set PI in shutdown mode */ + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) + return ret; + + val =3D (u8)ret; + val &=3D ~CHAN_MASK(chan0); + val &=3D ~CHAN_MASK(chan1); + + ret =3D i2c_smbus_write_byte_data(client, PORT_MODE_REG, val); + if (ret) + return ret; + + return 0; +} + +static int si3474_pi_get_chan_current(struct si3474_priv *priv, u8 chan) +{ + struct i2c_client *client; + u64 tmp_64; + s32 ret; + u8 reg; + + client =3D si3474_get_chan_client(priv, chan); + + /* Registers 0x30 to 0x3d */ + reg =3D CHAN_REG(PORT1_CURRENT_LSB_REG, chan); + + ret =3D i2c_smbus_read_word_data(client, reg); + if (ret < 0) + return ret; + + tmp_64 =3D ret * SI3474_NA_STEP; + + /* uA =3D nA / 1000 */ + tmp_64 =3D DIV_ROUND_CLOSEST_ULL(tmp_64, 1000); + return (int)tmp_64; +} + +static int si3474_pi_get_chan_voltage(struct si3474_priv *priv, u8 chan) +{ + struct i2c_client *client; + u32 val; + s32 ret; + u8 reg; + + client =3D si3474_get_chan_client(priv, chan); + + /* Registers 0x32 to 0x3f */ + reg =3D CHAN_REG(PORT1_VOLTAGE_LSB_REG, chan); + + ret =3D i2c_smbus_read_word_data(client, reg); + if (ret < 0) + return ret; + + val =3D ret * SI3474_UV_STEP; + + return (int)val; +} + +static int si3474_pi_get_voltage(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + s32 ret; + u8 chan0, chan1; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Check which channels are enabled*/ + ret =3D i2c_smbus_read_byte_data(client, POWER_STATUS_REG); + if (ret < 0) + return ret; + + /* Take voltage from the first enabled channel */ + if (ret & CHAN_BIT(chan0)) + ret =3D si3474_pi_get_chan_voltage(priv, chan0); + else if (ret & CHAN_BIT(chan1)) + ret =3D si3474_pi_get_chan_voltage(priv, chan1); + else + /* 'should' be no voltage in this case */ + return 0; + + return ret; +} + +static int si3474_pi_get_actual_pw(struct pse_controller_dev *pcdev, int i= d) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + u64 tmp_64; + u32 uV, uA; + s32 ret; + u8 chan0, chan1; + + if (id >=3D SI3474_MAX_CHANS) + return -ERANGE; + + ret =3D si3474_pi_get_voltage(&priv->pcdev, id); + + /* Do not read currents if voltage is 0 */ + if (ret <=3D 0) + return ret; + uV =3D ret; + + si3474_get_channels(priv, id, &chan0, &chan1); + + ret =3D si3474_pi_get_chan_current(priv, chan0); + if (ret < 0) + return ret; + uA =3D ret; + + ret =3D si3474_pi_get_chan_current(priv, chan1); + if (ret < 0) + return ret; + uA +=3D ret; + + tmp_64 =3D uV; + tmp_64 *=3D uA; + /* mW =3D uV * uA / 1000000000 */ + return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); +} + +static const struct pse_controller_ops si3474_ops =3D { + .setup_pi_matrix =3D si3474_setup_pi_matrix, + .pi_enable =3D si3474_pi_enable, + .pi_disable =3D si3474_pi_disable, + .pi_get_actual_pw =3D si3474_pi_get_actual_pw, + .pi_get_voltage =3D si3474_pi_get_voltage, + .pi_get_admin_state =3D si3474_pi_get_admin_state, + .pi_get_pw_status =3D si3474_pi_get_pw_status, +}; + +static void si3474_ancillary_i2c_remove(void *data) +{ + struct i2c_client *client =3D data; + + i2c_unregister_device(client); +} + +static int si3474_i2c_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct si3474_priv *priv; + s32 ret; + u8 fw_version; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_err(dev, "i2c check functionality failed\n"); + return -ENXIO; + } + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret =3D i2c_smbus_read_byte_data(client, VENDOR_IC_ID_REG); + if (ret < 0) + return ret; + + if (ret !=3D SI3474_DEVICE_ID) { + dev_err(dev, "Wrong device ID: 0x%x\n", ret); + return -ENXIO; + } + + ret =3D i2c_smbus_read_byte_data(client, FIRMWARE_REVISION_REG); + if (ret < 0) + return ret; + fw_version =3D ret; + + ret =3D i2c_smbus_read_byte_data(client, CHIP_REVISION_REG); + if (ret < 0) + return ret; + + dev_dbg(dev, "Chip revision: 0x%x, firmware version: 0x%x\n", + ret, fw_version); + + priv->client[0] =3D client; + i2c_set_clientdata(client, priv); + + priv->client[1] =3D i2c_new_ancillary_device(priv->client[0], "secondary", + priv->client[0]->addr + 1); + if (IS_ERR(priv->client[1])) + return PTR_ERR(priv->client[1]); + + ret =3D devm_add_action_or_reset(dev, si3474_ancillary_i2c_remove, priv->= client[1]); + if (ret < 0) { + dev_err(&priv->client[1]->dev, "Cannot register remove callback\n"); + return ret; + } + + ret =3D i2c_smbus_read_byte_data(priv->client[1], VENDOR_IC_ID_REG); + if (ret < 0) { + dev_err(&priv->client[1]->dev, "Cannot access secondary PSE controller\n= "); + return ret; + } + + if (ret !=3D SI3474_DEVICE_ID) { + dev_err(&priv->client[1]->dev, + "Wrong device ID for secondary PSE controller: 0x%x\n", ret); + return -ENXIO; + } + + priv->np =3D dev->of_node; + priv->pcdev.owner =3D THIS_MODULE; + priv->pcdev.ops =3D &si3474_ops; + priv->pcdev.dev =3D dev; + priv->pcdev.types =3D ETHTOOL_PSE_C33; + priv->pcdev.nr_lines =3D SI3474_MAX_CHANS; + + ret =3D devm_pse_controller_register(dev, &priv->pcdev); + if (ret) { + dev_err(dev, "Failed to register PSE controller: 0x%x\n", ret); + return ret; + } + + return 0; +} + +static const struct i2c_device_id si3474_id[] =3D { + { "si3474" }, + {} +}; +MODULE_DEVICE_TABLE(i2c, si3474_id); + +static const struct of_device_id si3474_of_match[] =3D { + { + .compatible =3D "skyworks,si3474", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, si3474_of_match); + +static struct i2c_driver si3474_driver =3D { + .probe =3D si3474_i2c_probe, + .id_table =3D si3474_id, + .driver =3D { + .name =3D "si3474", + .of_match_table =3D si3474_of_match, + }, +}; +module_i2c_driver(si3474_driver); + +MODULE_AUTHOR("Piotr Kubik "); +MODULE_DESCRIPTION("Skyworks Si3474 PoE PSE Controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0