From nobody Fri Apr 10 02:39:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE8E12FE591; Wed, 4 Mar 2026 17:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644298; cv=none; b=RfTVxTRcWM93nnqYyNrCp7P5kmvURGcNbTpv3MjQiF8YXV4lXlGKhPIuYTm67OCXGCcxjhgz4xk27cO0KlLs9OIDa3qwjaj5XJSjk9jVQUHdvYORVKUY6rwliftvI2T2yHz8c9cU+Erv12PeCRcXbRQk9PypfQ3CDrnVaP9LSkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644298; c=relaxed/simple; bh=ziHKF2arAv3Wx3iiRak95tXSruy5u/qt15Wv4H57xNA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFVYZhkp2dnjdtOAW7OezJpmq/YZUoC95x5IQdCQGRO2BBBvDfiClcuxWUUDWZgNMYrvUFocmLDHZCZMi/wH25P4WC8ygASa1LwpwXy0inKTJdcGwUwD77EVT9NqTeuceHhyS2bfrVYFm0ugNXpu+p9h+a85/+y9Slz2cvrXuvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00AE9C4CEF7; Wed, 4 Mar 2026 17:11:33 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/7] arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:02 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi index 352c96d144a84102..02e62d954e94905d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -152,10 +152,10 @@ qspi_clk: qspi-clk { timer { compatible =3D "arm,armv8-timer"; interrupt-parent =3D <&intc>; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 usbphy0: usbphy { --=20 2.43.0