From nobody Sat Oct 11 00:41:14 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8F22299A8E; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=eZWyfdDCoNeVawYRVw8atqD5+ryZAwIEAwvMxWiV1a6vFwOZVn0cj9nEG/jQ9runoVo+ktK5dibyCsbveSS0HBwtAZCx18fncImgneaWK5OUJufCgiqBqykoeNiDM0/nHEDLdRgVEDlhLyvq69Zsbrdx/Q++MokJCZizRjSrca4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=U1Hyh++FbbQjcYY3cPFX1njwwCp4wpvVjBJyLtaysnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fQycQk2DNwLVGqV7B1oKPunL/KUS6MAFpCh2AfX+opDD2bQ09E/G6sZqGLgNZCOj8DXXvK2/UHNk4HBzgAh9yQBKJ6MQSJ61z8RFf60NC0gm5tj1nfdnmt3L2HcgkJt+gEgPl0auEx2WJWYtANiPODkCBLu57+0MWPEFGMJNsIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jaR69CP1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jaR69CP1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 879BFC4CEF1; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=U1Hyh++FbbQjcYY3cPFX1njwwCp4wpvVjBJyLtaysnA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jaR69CP1bWvKjCN2leBeGttu1F2uZBdLwQap88HNEyBEAqFjHo5JM9XIc/PdQBwQC twdRAq5sCMgy/SauImsiUhk/UMR8u3wOl7jiOv5ZR1D9+LMYVNMeo5RYVWtUEc/5YH f62B4cqFYdtuAMaTs1rkfAVy2+rpCRums4wd49OB3gHXP2shHie6XAO5ac+SMPftXA FuKl3heDbXP4x1VdGKncioQEEaEmc/Q6K+HmjrCDmbLee2O8l56AF0RNizRV8Ov5io C48dx07oPzla02x8/03hhREBrhcX/4e/HDs4RGXNXregFk9JcyzZDs2xV2OWQQyXpd 2v5wX9xRo8tPw== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005EwM-36Ag; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 19/20] docs: hest: add new "etc/acpi_table_hest_addr" and update workflow Date: Thu, 12 Jun 2025 17:17:43 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" While the HEST layout didn't change, there are some internal changes related to how offsets are calculated and how memory error events are triggered. Update specs to reflect such changes. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- docs/specs/acpi_hest_ghes.rst | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst index c3e9f8d9a702..3d1b85d74b70 100644 --- a/docs/specs/acpi_hest_ghes.rst +++ b/docs/specs/acpi_hest_ghes.rst @@ -89,12 +89,21 @@ Design Details addresses in the "error_block_address" fields with a pointer to the respective "Error Status Data Block" in the "etc/hardware_errors" blob. =20 -(8) QEMU defines a third and write-only fw_cfg blob which is called - "etc/hardware_errors_addr". Through that blob, the firmware can send b= ack - the guest-side allocation addresses to QEMU. The "etc/hardware_errors_= addr" - blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER co= mmand - for the firmware. The firmware will write back the start address of - "etc/hardware_errors" blob to the fw_cfg file "etc/hardware_errors_add= r". +(8) QEMU defines a third and write-only fw_cfg blob to store the location + where the error block offsets, read ack registers and CPER records are + stored. + + Up to QEMU 9.2, the location was at "etc/hardware_errors_addr", and + contains a GPA for the beginning of "etc/hardware_errors". + + Newer versions place the location at "etc/acpi_table_hest_addr", + pointing to the GPA of the HEST table. + + Using above mentioned 'fw_cfg' files, the firmware can send back the + guest-side allocation addresses to QEMU. They contain a 8-byte entry. + QEMU generates a single WRITE_POINTER command for the firmware. The + firmware will write back the start address of either "etc/hardware_err= ors" + or HEST table at the corresponding fw_cfg file. =20 (9) When QEMU gets a SIGBUS from the kernel, QEMU writes CPER into corresp= onding "Error Status Data Block", guest memory, and then injects platform spe= cific @@ -105,8 +114,5 @@ Design Details kernel, on receiving notification, guest APEI driver could read the C= PER error and take appropriate action. =20 -(11) kvm_arch_on_sigbus_vcpu() uses source_id as index in "etc/hardware_er= rors" to - find out "Error Status Data Block" entry corresponding to error sourc= e. So supported - source_id values should be assigned here and not be changed afterward= s to make sure - that guest will write error into expected "Error Status Data Block" e= ven if guest was - migrated to a newer QEMU. +(11) kvm_arch_on_sigbus_vcpu() report RAS errors via a SEA notifications, + when a SIGBUS event is triggered. --=20 2.49.0