From nobody Thu Apr 2 06:28:46 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BF7F3EBF35; Thu, 5 Mar 2026 17:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732681; cv=none; b=Zbhg26JifdrNU3CBUmLm5d/YtcedlUCqW6iBtGvgpFOSix6OAwgfZzxVrCN1PznOPIzczRTmladuu7Gt1KE0OZD/AYP68uHChLPsu7WtqmbJlzfZ6vZksh2I+ES+4tN1yvxfOR0axLQhxkBS5R0q+w/hmMFKdw36ZG1OWILS98s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732681; c=relaxed/simple; bh=1aenzwDGDxj7/Xy0K7xK2VZ8ll7V/R5F1ZAMykoI7BM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WifR8ZOnzyX6/TR15s3y7l55kZLVzzImSO8UaqQ6XtoiVeyHhzFHg6TjA6erEjG4JRrulwNAl2jd3aUBylRa+NPpz8IoGfkjyCx9iCZoCaKqIwwszHurknotEK8lX7i6G4fvuYH64jErcn4Rd8TTMS2vo0GiWeNDoDAEIP8MaSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=X4NwnYXR; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="X4NwnYXR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772732680; x=1804268680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1aenzwDGDxj7/Xy0K7xK2VZ8ll7V/R5F1ZAMykoI7BM=; b=X4NwnYXR/chAu7rRuf6GoHH1FXyLBQ8M/Cp7jJpHThgzRj/NQrBfx4jl X+rwjpOAgmKdlrRvtXSMvKJTVYxnNewECpWADCNS74jvzWCnkS+micCVI KQovzI4x4lnv8VbkSTYFG/2UHKHWERcxDZBWjHRZtmOSVK0RwOpcDCPJo avCRtYe5T/IHZOkvE2m1LdvCp71dd3BqDf7vugPs/Of/m0Pch4sti+2YJ /xqULQ3wNxH1JpH2Amsk0RLFNIFe4D+Ms+CTzDN7nWdzsEvXwtLTV06n5 u8pwaNloxgqSA2dzAXcqH+bh5pG4XPCZ2MFn+2gHNd/HgcYl0Jz+8VKeh w==; X-CSE-ConnectionGUID: b5dDoaVyTA2stI8wj/0Psg== X-CSE-MsgGUID: kwecv7DPTuecj4Z5OOT8Yg== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="77431574" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="77431574" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:37 -0800 X-CSE-ConnectionGUID: TI3CSsrbTZCmStv+UxZP4Q== X-CSE-MsgGUID: z8MdqYnZRdiexiuXckp1jA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="223447877" Received: from mdroper-mobl2.amr.corp.intel.com (HELO localhost) ([10.124.220.244]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:37 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , Sean Christopherson , linux-kernel@vger.kernel.org Subject: [PATCH v2 12/36] KVM: nVMX: Add tertiary VM-execution control VMCS support Date: Thu, 5 Mar 2026 09:43:52 -0800 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata Support tertiary processor-based VM-execution control VMCS field. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/hyperv.c | 10 ++++++++++ arch/x86/kvm/vmx/nested.c | 17 +++++++++++++++++ arch/x86/kvm/vmx/nested.h | 7 +++++++ arch/x86/kvm/vmx/vmcs12.c | 1 + arch/x86/kvm/vmx/vmcs12.h | 3 ++- 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/hyperv.c b/arch/x86/kvm/vmx/hyperv.c index 2731c2e4b0e5..70e210472681 100644 --- a/arch/x86/kvm/vmx/hyperv.c +++ b/arch/x86/kvm/vmx/hyperv.c @@ -166,6 +166,12 @@ static bool nested_evmcs_is_valid_controls(enum evmcs_= ctrl_type ctrl_type, return !(val & ~evmcs_get_supported_ctls(ctrl_type)); } =20 +static bool nested_evmcs_is_valid_controls64(enum evmcs_ctrl_type ctrl_typ= e, + u64 val) +{ + return !(val & ~evmcs_get_supported_ctls(ctrl_type)); +} + int nested_evmcs_check_controls(struct vmcs12 *vmcs12) { if (CC(!nested_evmcs_is_valid_controls(EVMCS_PINCTRL, @@ -188,6 +194,10 @@ int nested_evmcs_check_controls(struct vmcs12 *vmcs12) vmcs12->vm_entry_controls))) return -EINVAL; =20 + if (CC(!nested_evmcs_is_valid_controls64(EVMCS_3RDEXEC, + vmcs12->tertiary_vm_exec_control))) + return -EINVAL; + /* * VM-Func controls are 64-bit, but KVM currently doesn't support any * controls in bits 63:32, i.e. dropping those bits on the consistency diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index be6b92b3c66a..1bd5e164e285 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -1815,6 +1815,7 @@ static void copy_enlightened_to_vmcs12(struct vcpu_vm= x *vmx, u32 hv_clean_fields vmcs12->vm_exit_controls =3D evmcs->vm_exit_controls; vmcs12->secondary_vm_exec_control =3D evmcs->secondary_vm_exec_control; + vmcs12->tertiary_vm_exec_control =3D 0; } =20 if (unlikely(!(hv_clean_fields & @@ -2511,6 +2512,17 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vm= x, struct loaded_vmcs *vmcs0 secondary_exec_controls_set(vmx, exec_control); } =20 + /* + * TERTIARY EXEC CONTROLS + */ + if (cpu_has_tertiary_exec_ctrls()) { + u64 ctls =3D 0; + + /* guest apic timer virtualization will come */ + + tertiary_exec_controls_set(vmx, ctls); + } + /* * ENTRY CONTROLS * @@ -2969,6 +2981,11 @@ static int nested_check_vm_execution_controls(struct= kvm_vcpu *vcpu, vmx->nested.msrs.secondary_ctls_high))) return -EINVAL; =20 + if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) && + CC(!vmx_control64_verify(vmcs12->tertiary_vm_exec_control, + vmx->nested.msrs.tertiary_ctls))) + return -EINVAL; + if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) || nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) || nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) || diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 8c25054a710e..52bf035bcc03 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -175,6 +175,13 @@ static inline bool nested_cpu_has2(struct vmcs12 *vmcs= 12, u32 bit) (vmcs12->secondary_vm_exec_control & bit); } =20 +static inline bool nested_cpu_has3(struct vmcs12 *vmcs12, u64 bit) +{ + return (vmcs12->cpu_based_vm_exec_control & + CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) && + (vmcs12->tertiary_vm_exec_control & bit); +} + static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) { return vmcs12->pin_based_vm_exec_control & diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c index 1ebe67c384ad..e2e2a99c8aa9 100644 --- a/arch/x86/kvm/vmx/vmcs12.c +++ b/arch/x86/kvm/vmx/vmcs12.c @@ -38,6 +38,7 @@ static const u16 kvm_supported_vmcs12_field_offsets[] __i= nitconst =3D { FIELD64(PML_ADDRESS, pml_address), FIELD64(TSC_OFFSET, tsc_offset), FIELD64(TSC_MULTIPLIER, tsc_multiplier), + FIELD64(TERTIARY_VM_EXEC_CONTROL, tertiary_vm_exec_control), FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), FIELD64(APIC_ACCESS_ADDR, apic_access_addr), FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h index 8c9d4c22b960..b7d30a2cf23f 100644 --- a/arch/x86/kvm/vmx/vmcs12.h +++ b/arch/x86/kvm/vmx/vmcs12.h @@ -71,7 +71,7 @@ struct __packed vmcs12 { u64 pml_address; u64 encls_exiting_bitmap; u64 tsc_multiplier; - u64 padding64[1]; /* room for future expansion */ + u64 tertiary_vm_exec_control; /* * To allow migration of L1 (complete with its L2 guests) between * machines of different natural widths (32 or 64 bit), we cannot have @@ -262,6 +262,7 @@ static inline void vmx_check_vmcs12_offsets(void) CHECK_OFFSET(pml_address, 312); CHECK_OFFSET(encls_exiting_bitmap, 320); CHECK_OFFSET(tsc_multiplier, 328); + CHECK_OFFSET(tertiary_vm_exec_control, 336); CHECK_OFFSET(cr0_guest_host_mask, 344); CHECK_OFFSET(cr4_guest_host_mask, 352); CHECK_OFFSET(cr0_read_shadow, 360); --=20 2.45.2