From nobody Wed Feb 11 06:32:27 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 037A11E8329; Fri, 9 Jan 2026 03:03:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767927833; cv=none; b=aSiqvi13h8ZHDcL+p0PqgNEdVFVNuNtnbCxhRZbZcUkhDkpPX3fz5uuP/SKudZ9WHZX1DxSYO7R4vOvl0tiV5xnRvCHjv8cuhwOFfWwckxEg6RxHUluTTp3SNwy1LKWOgcmKzQTMJ5ulfkPC63T6dj3TlUp3Y3tQECOQyUNsi7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767927833; c=relaxed/simple; bh=fFQh76+m+BUPRidLALObSIy1ryFNPjOKKoEZgbiNkTg=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jN8h8Ac/0hqGnJ0Z0nEf217b7ujh6uBvS7h8doESo5exnyB2RLdLNmwgKg3prjHTPU4YL3frgKH7ShMTsIIPGuvll4WUWaJC52ZycGbpiwab5G6WCu9d1T7hkKNUKGdseSBwRqDX+5f0dliEnKy9dr9BGFyiKv2yKyizHpZC/d8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1ve2mw-000000005lV-3bcD; Fri, 09 Jan 2026 03:03:46 +0000 Date: Fri, 9 Jan 2026 03:03:44 +0000 From: Daniel Golle To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Vladimir Oltean , Michael Klein , Aleksander Jan Bajkowski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net: phy: realtek: demystify PHYSR register location Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Turns out that register address RTL_VND2_PHYSR (0xa434) maps to Clause-22 register MII_RESV2. Use that to get rid of yet another magic number, and rename access macros accordingly. Signed-off-by: Daniel Golle --- drivers/net/phy/realtek/realtek_main.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realt= ek/realtek_main.c index d07d60bc1ce34..5712372c71f91 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -178,12 +178,12 @@ #define RTL9000A_GINMR 0x14 #define RTL9000A_GINMR_LINK_STATUS BIT(4) =20 -#define RTL_VND2_PHYSR 0xa434 -#define RTL_VND2_PHYSR_DUPLEX BIT(3) -#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) -#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) -#define RTL_VND2_PHYSR_MASTER BIT(11) -#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR= _SPEEDH) +#define RTL_PHYSR MII_RESV2 +#define RTL_PHYSR_DUPLEX BIT(3) +#define RTL_PHYSR_SPEEDL GENMASK(5, 4) +#define RTL_PHYSR_SPEEDH GENMASK(10, 9) +#define RTL_PHYSR_MASTER BIT(11) +#define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) =20 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 @@ -1102,12 +1102,12 @@ static void rtlgen_decode_physr(struct phy_device *= phydev, int val) * 0: Half Duplex * 1: Full Duplex */ - if (val & RTL_VND2_PHYSR_DUPLEX) + if (val & RTL_PHYSR_DUPLEX) phydev->duplex =3D DUPLEX_FULL; else phydev->duplex =3D DUPLEX_HALF; =20 - switch (val & RTL_VND2_PHYSR_SPEED_MASK) { + switch (val & RTL_PHYSR_SPEED_MASK) { case 0x0000: phydev->speed =3D SPEED_10; break; @@ -1135,7 +1135,7 @@ static void rtlgen_decode_physr(struct phy_device *ph= ydev, int val) * 1: Master Mode */ if (phydev->speed >=3D 1000) { - if (val & RTL_VND2_PHYSR_MASTER) + if (val & RTL_PHYSR_MASTER) phydev->master_slave_state =3D MASTER_SLAVE_STATE_MASTER; else phydev->master_slave_state =3D MASTER_SLAVE_STATE_SLAVE; @@ -1155,8 +1155,7 @@ static int rtlgen_read_status(struct phy_device *phyd= ev) if (!phydev->link) return 0; =20 - val =3D phy_read_paged(phydev, RTL822X_VND2_TO_PAGE(RTL_VND2_PHYSR), - RTL822X_VND2_TO_PAGE_REG(RTL_VND2_PHYSR)); + val =3D phy_read(phydev, RTL_PHYSR); if (val < 0) return val; =20 @@ -1622,7 +1621,8 @@ static int rtl822x_c45_read_status(struct phy_device = *phydev) } =20 /* Read actual speed from vendor register. */ - val =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); + val =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, + RTL822X_VND2_C22_REG(RTL_PHYSR)); if (val < 0) return val; =20 --=20 2.52.0