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Co-developed-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Tomasz Jeznach --- .../bindings/iommu/riscv,iommu.yaml | 147 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Doc= umentation/devicetree/bindings/iommu/riscv,iommu.yaml new file mode 100644 index 000000000000..5d015eeb06d0 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V IOMMU Architecture Implementation + +maintainers: + - Tomasz Jeznach + +description: | + The RISC-V IOMMU provides memory address translation and isolation for + input and output devices, supporting per-device translation context, + shared process address spaces including the ATS and PRI components of + the PCIe specification, two stage address translation and MSI remapping. + It supports identical translation table format to the RISC-V address + translation tables with page level access and protection attributes. + Hardware uses in-memory command and fault reporting queues with wired + interrupt or MSI notifications. + + Visit https://github.com/riscv-non-isa/riscv-iommu for more details. + + For information on assigning RISC-V IOMMU to its peripheral devices, + see generic IOMMU bindings. + +properties: + # For PCIe IOMMU hardware compatible property should contain the vendor + # and device ID according to the PCI Bus Binding specification. + # Since PCI provides built-in identification methods, compatible is not + # actually required. For non-PCIe hardware implementations 'riscv,iommu' + # should be specified along with 'reg' property providing MMIO location. + compatible: + oneOf: + - items: + - enum: + - qemu,riscv-iommu + - const: riscv,iommu + - items: + - enum: + - pci1efd,edf1 + - const: riscv,pci-iommu + + reg: + maxItems: 1 + description: + For non-PCI devices this represents base address and size of for the + IOMMU memory mapped registers interface. + For PCI IOMMU hardware implementation this should represent an addre= ss + of the IOMMU, as defined in the PCI Bus Binding reference. + + '#iommu-cells': + const: 1 + description: + The single cell describes the requester id emitted by a master to the + IOMMU. + + interrupts: + minItems: 1 + maxItems: 4 + description: + Wired interrupt vectors available for RISC-V IOMMU to notify the + RISC-V HARTS. The cause to interrupt vector is software defined + using IVEC IOMMU register. + + msi-parent: true + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - '#iommu-cells' + +additionalProperties: false + +examples: + - |+ + /* Example 1 (IOMMU device with wired interrupts) */ + #include + + iommu1: iommu@1bccd000 { + compatible =3D "qemu,riscv-iommu", "riscv,iommu"; + reg =3D <0x1bccd000 0x1000>; + interrupt-parent =3D <&aplic_smode>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>, + <35 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells =3D <1>; + }; + + /* Device with two IOMMU device IDs, 0 and 7 */ + master1 { + iommus =3D <&iommu1 0>, <&iommu1 7>; + }; + + - |+ + /* Example 2 (IOMMU device with shared wired interrupt) */ + #include + + iommu2: iommu@1bccd000 { + compatible =3D "qemu,riscv-iommu", "riscv,iommu"; + reg =3D <0x1bccd000 0x1000>; + interrupt-parent =3D <&aplic_smode>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells =3D <1>; + }; + + - |+ + /* Example 3 (IOMMU device with MSIs) */ + iommu3: iommu@1bcdd000 { + compatible =3D "qemu,riscv-iommu", "riscv,iommu"; + reg =3D <0x1bccd000 0x1000>; + msi-parent =3D <&imsics_smode>; + #iommu-cells =3D <1>; + }; + + - |+ + /* Example 4 (IOMMU PCIe device with MSIs) */ + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@30000000 { + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x0 0x30000000 0x0 0x1000000>; + ranges =3D <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0= f000000>; + + /* + * The IOMMU manages all functions in this PCI domain except + * itself. Omit BDF 00:01.0. + */ + iommu-map =3D <0x0 &iommu0 0x0 0x8>, + <0x9 &iommu0 0x9 0xfff7>; + + /* The IOMMU programming interface uses slot 00:01.0 */ + iommu0: iommu@1,0 { + compatible =3D "pci1efd,edf1", "riscv,pci-iommu"; + reg =3D <0x800 0 0 0 0>; + #iommu-cells =3D <1>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a097afd76ded..839554c5ff06 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19885,6 +19885,13 @@ F: arch/riscv/ N: riscv K: riscv =20 +RISC-V IOMMU +M: Tomasz Jeznach +L: iommu@lists.linux.dev +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara --=20 2.34.1