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Sun, 15 Feb 2026 00:55:39 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Neil Armstrong , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH 1/4] arm64: dts: mt8167: Reorder nodes according to mmio address Date: Sun, 15 Feb 2026 08:53:53 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding display nodes. No other changes. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++------------ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts= /mediatek/mt8167.dtsi index 2374c0953057..27cf32d7ae35 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -29,12 +29,6 @@ infracfg: infracfg@10001000 { #clock-cells =3D <1>; }; =20 - apmixedsys: apmixedsys@10018000 { - compatible =3D "mediatek,mt8167-apmixedsys", "syscon"; - reg =3D <0 0x10018000 0 0x710>; - #clock-cells =3D <1>; - }; - scpsys: syscon@10006000 { compatible =3D "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg =3D <0 0x10006000 0 0x1000>; @@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN { }; }; =20 - imgsys: syscon@15000000 { - compatible =3D "mediatek,mt8167-imgsys", "syscon"; - reg =3D <0 0x15000000 0 0x1000>; - #clock-cells =3D <1>; - }; - - vdecsys: syscon@16000000 { - compatible =3D "mediatek,mt8167-vdecsys", "syscon"; - reg =3D <0 0x16000000 0 0x1000>; - #clock-cells =3D <1>; - }; - pio: pinctrl@1000b000 { compatible =3D "mediatek,mt8167-pinctrl"; reg =3D <0 0x1000b000 0 0x1000>; @@ -124,12 +106,36 @@ pio: pinctrl@1000b000 { interrupts =3D ; }; =20 + apmixedsys: apmixedsys@10018000 { + compatible =3D "mediatek,mt8167-apmixedsys", "syscon"; + reg =3D <0 0x10018000 0 0x710>; + #clock-cells =3D <1>; + }; + + iommu: m4u@10203000 { + compatible =3D "mediatek,mt8167-m4u"; + reg =3D <0 0x10203000 0 0x1000>; + mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>; + interrupts =3D ; + #iommu-cells =3D <1>; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8167-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb0: larb@14016000 { + compatible =3D "mediatek,mt8167-smi-larb"; + reg =3D <0 0x14016000 0 0x1000>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + }; + smi_common: smi@14017000 { compatible =3D "mediatek,mt8167-smi-common"; reg =3D <0 0x14017000 0 0x1000>; @@ -139,14 +145,10 @@ smi_common: smi@14017000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; }; =20 - larb0: larb@14016000 { - compatible =3D "mediatek,mt8167-smi-larb"; - reg =3D <0 0x14016000 0 0x1000>; - mediatek,smi =3D <&smi_common>; - clocks =3D <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names =3D "apb", "smi"; - power-domains =3D <&spm MT8167_POWER_DOMAIN_MM>; + imgsys: syscon@15000000 { + compatible =3D "mediatek,mt8167-imgsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; }; =20 larb1: larb@15001000 { @@ -159,6 +161,12 @@ larb1: larb@15001000 { power-domains =3D <&spm MT8167_POWER_DOMAIN_ISP>; }; =20 + vdecsys: syscon@16000000 { + compatible =3D "mediatek,mt8167-vdecsys", "syscon"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; + }; + larb2: larb@16010000 { compatible =3D "mediatek,mt8167-smi-larb"; reg =3D <0 0x16010000 0 0x1000>; @@ -168,13 +176,5 @@ larb2: larb@16010000 { clock-names =3D "apb", "smi"; power-domains =3D <&spm MT8167_POWER_DOMAIN_VDEC>; }; - - iommu: m4u@10203000 { - compatible =3D "mediatek,mt8167-m4u"; - reg =3D <0 0x10203000 0 0x1000>; - mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>; - interrupts =3D ; - #iommu-cells =3D <1>; - }; }; }; --=20 2.43.0