From nobody Sun Apr 5 16:32:59 2026 Received: from mail-244123.protonmail.ch (mail-244123.protonmail.ch [109.224.244.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A28E344054 for ; Fri, 20 Feb 2026 12:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771591494; cv=none; b=bSZFNUKXLE9Fo0LaO7ohBHQrpHx8RFZzj+jpqsy/GRRD0lJDAaTt7vyjfs8dXTqzFlI9PFw2v63wASflMTo7VlaNLjCJ4byF3J0hzjLo0ikta/FGZ8XjDnntcO2PZ7Lus5yZ3WfOouKgc5qeBi3/P1Te4W0m/nsAP7vHZ/SD5bU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771591494; c=relaxed/simple; bh=6u5IeIgvjbDjaxjJTuRXTmR6NGkknxCa5fR2Rwz+LWc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tFnkNXS2uzMQRFWK+TdMYd1QlJDAJNA2q4/yWCCRVqrco/JpX1vzGvN+BotqXHl288cRG+MMrzy50LpCAoBSOyzYIjfuYmDYJLdaPkm84mtwEiKfkMg2chuTcu5rssjl4A4BFWcJNAUWk/6ZhmDsPQVXr+IXfMxcJowZZLtzq/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=duPk0HQC; arc=none smtp.client-ip=109.224.244.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="duPk0HQC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1771591485; x=1771850685; bh=8dY8pcaRxOZ1sCdxB4dipkfHn87abpoNsKCXX3e6sA4=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=duPk0HQCa7RpiMdt1qbkfvCrZxOHkzMtmT0R8vqy0qM/+st/6I+LVd+FcDxuflMdh emSSnWcd5+85uiNTmMbix8W35Dzz+/FJNz1zmdtQM2WiPTutPZUVJKjupy8DY4Q304 HuL2+GZjXiApd50GvOQr+D8MTqG/hpZcyRbw+NqYBYz4+s2ydhJ9poWY9iWcNfY3CG N6+vylw7tsSnFLPswizHrJ/1tBlyQzoQPwGQ8gHsvL2TWhp0KjwBs5jX2gNtR6EDF5 ucWNe7XGMRij5ZOq1HUHtCMSplUb/BaxeY80moFCAONYFQKQhJUOgAnS8PPMhZYbVI LFuLGtFtd95mQ== Date: Fri, 20 Feb 2026 12:44:41 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Farrah Chen , Maciej Wieczor-Retman , stable@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/3] x86/cpu: Clear feature bits disabled at compile-time Message-ID: In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: f321113ee7ba66fe27866265a4af1d7666746fec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman If some config options are disabled during compile time, they still are enumerated in macros that use the x86_capability bitmask - cpu_has() or this_cpu_has(). The features are also visible in /proc/cpuinfo even though they are not enabled - which is contrary to what the documentation states about the file. Examples of such feature flags are lam, fred, sgx, ibrs_enhanced, split_lock_detect, user_shstk, avx_vnni and enqcmd. Once the cpu_caps_cleared array is initialized with the autogenerated disabled bitmask apply_forced_caps() will clear the corresponding bits in boot_cpu_data.x86_capability[] and other secondary cpus' cpu_data.x86_capability[]. Thus features disabled at compile time won't show up in /proc/cpuinfo. Reported-by: Farrah Chen Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D220348 Signed-off-by: Maciej Wieczor-Retman Cc: # 6.18.x --- Changelog v6: - Remove patch message portions that are not just describing the diff. arch/x86/kernel/cpu/common.c | 3 ++- arch/x86/tools/cpufeaturemasks.awk | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e7ab22fce3b5..8d12c5722245 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -732,7 +732,8 @@ static const char *table_lookup_model(struct cpuinfo_x8= 6 *c) } =20 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long= )); +__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long= )) =3D + DISABLED_MASK_INITIALIZER; __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); =20 #ifdef CONFIG_X86_32 diff --git a/arch/x86/tools/cpufeaturemasks.awk b/arch/x86/tools/cpufeature= masks.awk index 173d5bf2d999..b7f4e775a365 100755 --- a/arch/x86/tools/cpufeaturemasks.awk +++ b/arch/x86/tools/cpufeaturemasks.awk @@ -82,6 +82,12 @@ END { } printf " 0\t\\\n"; printf "\t) & (1U << ((x) & 31)))\n\n"; + + printf "\n#define %s_MASK_INITIALIZER\t\t\t\\", s; + printf "\n\t{\t\t\t\t\t\t\\"; + for (i =3D 0; i < ncapints; i++) + printf "\n\t\t%s_MASK%d,\t\t\t\\", s, i; + printf "\n\t}\n\n"; } =20 printf "#endif /* _ASM_X86_CPUFEATUREMASKS_H */\n"; --=20 2.53.0