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Sat, 8 Nov 2025 00:08:21 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v5 4/7] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Date: Sat, 8 Nov 2025 00:08:05 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DE:EE_|LV8PR12MB9715:EE_ X-MS-Office365-Filtering-Correlation-Id: 31d7729b-2dd7-4f60-1aff-08de1e9e048b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5rKbvqDbuXny1Wk06p6gi5XtqV4oS6UF100bA8Puxcf5/PIdWEtJAUb+oXv+?= =?us-ascii?Q?til1n9xDqK4Ik5NQzsa/51ahdnlUY7eR4522MavgVvbDcH1HBz+Aa0VkJGe3?= =?us-ascii?Q?2SmucIG8t1vkfLztwjETh38loBJ1f5R2sq0RZW1mye2yL97ktNHCHKMJoHuN?= =?us-ascii?Q?Fx68x8mzxnF1nDXzMFPdvk6pJM6FlfosXXzcGA0vtWCyCLz77FPN+iaE+EpE?= =?us-ascii?Q?92DsP/DOQPKLNtP2j2Xf9Ybo2siyOtTnOwf+aN5Wtbb3n3BTS7byMtUKM5h9?= =?us-ascii?Q?kYke1CDNOf9vmMG5jABjS+XT/h58fJW2bBY3OTwfW/pLQwl+3olyu4QoKUUw?= =?us-ascii?Q?Cgk5AfEm2GjjvIq6LIknjrO/ahOGcqO0ig7oz+WomNl469Xr1SmlBy+r0Vsa?= =?us-ascii?Q?ZI1Ph1iTy5CpFVWYpq9kwzWAc8OV+n+oSSnD+DfNkHq5Gnl+k3bOEcD52u1Y?= =?us-ascii?Q?AEqaUPN+0OXHbM0nSG+biBInWDBGE7TI9txNzlpfoRx3pZctpPhFeZzfeew4?= =?us-ascii?Q?OZleupJW7ufNAXb7NVlg3UV5am7Wao9a8S1ECZ3fEQaZoylzUJ5LI5cI6Ve8?= =?us-ascii?Q?3MFRLaP/y6feTlcugvth87gSGuAXtP/Vu1CZ0DWl34X8irvMxRLncrq7rNqV?= =?us-ascii?Q?SupkEmoa2CEojR4LoBPtpm2yF2v62EuE2vEG7VeX07exrSfx9iiGeQ9BWU01?= =?us-ascii?Q?ENa8pp8baJTmf+kJKMPq/Z5i/BHJkTATa/1b2tSXLASw5IeDOpAuUVgDxyD0?= =?us-ascii?Q?FYr4cA6KjQvjEhdNEy3itytce5jUMEsC0iAz6OZYdxp1V+gVohUUvl7lUVaB?= =?us-ascii?Q?gd/cYYjZl9uvCW0cA9YJf/Qwp+jcnjlcX5S+Z9DghHICsLHQH2LpiJ5lq6l3?= =?us-ascii?Q?FpeSY+v/jJT07BAQUBxMXscIZ/761iwlOYBwoBy9gLgValutklzrXoq0Bi8o?= =?us-ascii?Q?22e6bdob3vrlnjGN3M8PYzjX/H2yyZGVhjZHipwERBSE92G0Tqjm6AyMYAEg?= =?us-ascii?Q?8dNmmDkaypG+Q3lCaO2J9kUSxQ93fyvmB83hEAP9ZAylhX4P+oD2Cj9xS5DQ?= =?us-ascii?Q?jF12B8sqEEq+3VFbqHrfTnL5YZ6DXyXvegMpv0M+nZXNOllZHYUeIPNp2Pnv?= =?us-ascii?Q?HTfLhFPxH9p4u0dZU0ZC8qAMEG6daBPpIFTmPZfjLsczMhHtrsmRKgwDhU07?= =?us-ascii?Q?P4E2sIFL6py4cToybyJNXfALHTPGmpfryoF0uKQUQAhVUT38QBF64IsewxQ4?= =?us-ascii?Q?Wrry1WaYEIUDiZg9sOpSvFtJ8fER0YDZkj5MxyWWCWg0Gl4mLs6lRmIwNxBn?= =?us-ascii?Q?M9t20OOHR9o/hDcIyyKQs5SIQR7F23Mm07cCU2rE8w6Ndu2BFetElUkbk0/v?= =?us-ascii?Q?MQ5QqUWku27tqSsgwWPLRZePsE2rPalAb7RzvrbT/7n2pbrsjvN7f/aCf97f?= =?us-ascii?Q?hEjq/IYj/FOUL4qFUelDIRDsUhLKcDb4rnrMS7KLIbyH71hKug5wNrKyisM7?= =?us-ascii?Q?D1LcgWLyCqK3K5JMFRyJMpDp8QOwQE2lq9bdJC/955HJXZfA9gBYMynov6kf?= =?us-ascii?Q?w7o6MesNyWS/WYYw6lM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2025 08:08:36.0989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31d7729b-2dd7-4f60-1aff-08de1e9e048b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9715 Content-Type: text/plain; charset="utf-8" When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Sort fwspec->ids in an ascending order to fit to the arm_smmu_invs_merge() function. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 +++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 757158b9ea655..7b81a82c0dfe4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -922,6 +922,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8266d0839a927..26b8492a13f20 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3693,12 +3693,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu= _device *smmu, u32 sid) return 0; } =20 +static int arm_smmu_ids_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct iommu_fwspec, ids[0]) *l =3D _l; + const typeof_member(struct iommu_fwspec, ids[0]) *r =3D _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret =3D 0; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool ats_supported =3D dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); =20 master->streams =3D kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3706,6 +3716,21 @@ static int arm_smmu_insert_master(struct arm_smmu_de= vice *smmu, return -ENOMEM; master->num_streams =3D fwspec->num_ids; =20 + if (!ats_supported) { + /* Base case has 1 ASID entry or maximum 2 VMID entries */ + master->build_invs =3D arm_smmu_invs_alloc(2); + } else { + /* Put the ids into order for sorted to_merge/to_unref arrays */ + sort_nonatomic(fwspec->ids, fwspec->num_ids, + sizeof(fwspec->ids[0]), arm_smmu_ids_cmp, NULL); + /* ATS case adds num_ids of entries, on top of the base case */ + master->build_invs =3D arm_smmu_invs_alloc(2 + fwspec->num_ids); + } + if (IS_ERR(master->build_invs)) { + kfree(master->streams); + return PTR_ERR(master->build_invs); + } + mutex_lock(&smmu->streams_mutex); for (i =3D 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream =3D &master->streams[i]; @@ -3743,6 +3768,7 @@ static int arm_smmu_insert_master(struct arm_smmu_dev= ice *smmu, for (i--; i >=3D 0; i--) rb_erase(&master->streams[i].node, &smmu->streams); kfree(master->streams); + kfree(master->build_invs); } mutex_unlock(&smmu->streams_mutex); =20 @@ -3764,6 +3790,7 @@ static void arm_smmu_remove_master(struct arm_smmu_ma= ster *master) mutex_unlock(&smmu->streams_mutex); =20 kfree(master->streams); + kfree(master->build_invs); } =20 static struct iommu_device *arm_smmu_probe_device(struct device *dev) --=20 2.43.0