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Sun, 7 Dec 2025 12:49:48 -0800 From: Nicolin Chen To: , , CC: , , , , , , Subject: [PATCH rc v2 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Date: Sun, 7 Dec 2025 12:49:16 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|CY1PR12MB9673:EE_ X-MS-Office365-Filtering-Correlation-Id: d3ed688a-5e52-4ea6-b702-08de35d22e45 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nQJeB9vooUX9pa+xCsk11ZlNL8R2U2WUrFpx37rZ5L6Xvz+aih2kaF0nqYYd?= =?us-ascii?Q?e+POfrOk2tF0NdMeZRxnpkEqeg1a15kcjNOcyek0ZkbxdBx/vsFcZnN6c7Py?= =?us-ascii?Q?wvVjO+0EVHm6zr1xIp9rVC1ampw2nUItKbBC9liyGQ/QlZ0b6/WLB2HcLg3y?= =?us-ascii?Q?AQGaPqUS31NcUnoY8gxamsiFb8gEqoZsm5IkzxU/X7AiZU/SOyz4hif4JJsE?= =?us-ascii?Q?vh5+qIRJA5iuDarurEe16HyTa017RdnYnij+47SqcTQtTtazOfDLZaR20UIT?= =?us-ascii?Q?EOHLWKLy3/yhr/I0xDxpDZ0rjuFc2pI7emIal87hHPMiOGbG+JgqnRBKPi81?= =?us-ascii?Q?ZaF4Xk1gcomTQAoyy3muN8Ld1/x9cu+gsw63K65RdYVS/sFsGyvfhFCKCQ6b?= =?us-ascii?Q?pvnalvD5/MyQE3h2o+Z/XMAAhBpjqh5ejNZM47a29bd3tOKsmuCyWSO/D/7u?= =?us-ascii?Q?Bdmu5Lj3SIWATYLuzajZa00GM8G+IIPq1tpI7nNJc3/CMo4CAeh+t+ENgDNV?= =?us-ascii?Q?cGkVEsF/B/WgWrOm0hsdgt9gomn2KVP6WuImCsJnHkxUd+XpuD7Ff71iEg5v?= =?us-ascii?Q?4LTMZufDTC6Y6DwIFQ6iV3kPMaZX29zB22aRYDgalk2MuwSuCVxo77oRE6Zo?= =?us-ascii?Q?td3EFJ5WFEzosmWJaahulUhsCKeoDimTW5VS6iy4jCowvgllFex+W3dVgTaB?= =?us-ascii?Q?MXNikxoIlQKnL/eq5TxmS4+m5Ax5JNdnaF/4VhC+36Tbz53R+baXHFnCmWmU?= =?us-ascii?Q?ZL82nxWGxdoFX+xajcRl3cQJ8FtGNJhI/jcyqrrxET4CFHuZJD0knubFYUos?= =?us-ascii?Q?KGsVsbrBVz5ziCNCX6ZPiO2AQXLHadGfTPAMFXgrvli+4pmGGE5SVNGAwuQ6?= =?us-ascii?Q?6KeP68fW002i32D3EEP6EOB+x3+S1VGGqsREAkQUsbQ+QYdSBp0Gd/6tbQ8K?= =?us-ascii?Q?tn+LIiBgsH9Fy9Ts6ANEvAcVuTTI+JdiabCpCPay8CTV+clBJpYsOnuOTua2?= =?us-ascii?Q?zyJ9S5TSll49/rWHiiyKKTKPdfLeiiDhw3yUruM3c5M+CXfbaJMsFrcbkgEP?= =?us-ascii?Q?PkpobXBQVdRIndYNfs5ACiuwC/L3cS8Zf8xkQWpPhY27BNBGTmima6t+hhiK?= =?us-ascii?Q?rS43r/6wgKv6semqnCThurvK7qvwBIZLbGdB+QsaFYLOBDvLwuOqMtU71nKw?= =?us-ascii?Q?UgvQwNrN2+6Py10rPQRzaHmPNrObw3BILa9FbepLV6g//iwugszsnNVSWkR4?= =?us-ascii?Q?LPckSuIxwx+a8VOCthT+nj3lzSs+ZvJTGafiLSYxZFp0Z503GpHWfW4KPxMp?= =?us-ascii?Q?gPxVzB8Oslp92j/FprWzCBjjn8CYTDMjMIWsvwLflItqGOPkroIe4vXq9t3t?= =?us-ascii?Q?FvlLz/aqloiBWNbxe1pNJuIoX+Mz2XxWHeI2zbnQ1KtAktvG/GXfUurHPI8I?= =?us-ascii?Q?J1YKMrP68ltWs/NUPGHZkGLVEu8ImPyV+z5Ypl3WPvTALuxzqTjfoNxl25eu?= =?us-ascii?Q?SArMmBXa9cQOnWFrlA8TiE3+ZNgeid1Qq1QhpdzJhYGx2gLcJjzqcG8+oReF?= =?us-ascii?Q?XjoxxbgKGdxzIBiBjW4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2025 20:49:56.7436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3ed688a-5e52-4ea6-b702-08de35d22e45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9673 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Signed-off-by: Nicolin Chen Reviewed-by: Shuai Xue --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 3556e65cf9ac..1672e75ebffc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -555,6 +555,65 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void arm_smmu_test_make_nested_cdtable_ste( + struct arm_smmu_ste *ste, unsigned int s1dss, const dma_addr_t dma_addr, + enum arm_smmu_test_master_feat feat) +{ + bool stall_enabled =3D feat & ARM_SMMU_MASTER_TEST_STALL; + bool ats_enabled =3D feat & ARM_SMMU_MASTER_TEST_ATS; + struct arm_smmu_ste s1ste; + + struct arm_smmu_master master =3D { + .ats_enabled =3D ats_enabled, + .cd_table.cdtab_dma =3D dma_addr, + .cd_table.s1cdmax =3D 0xFF, + .cd_table.s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2, + .smmu =3D &smmu, + .stall_enabled =3D stall_enabled, + }; + + arm_smmu_test_make_s2_ste(ste, ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_make_cdtable_ste(&s1ste, &master, ats_enabled, s1dss); + + ste->data[0] =3D cpu_to_le64( + STRTAB_STE_0_V | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[0] |=3D s1ste.data[0] & ~cpu_to_le64(STRTAB_STE_0_CFG); + ste->data[1] |=3D s1ste.data[1]; + /* Merge events for DoS mitigations on eventq */ + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_nested_cdtable_ste(&s1_ste, + STRTAB_STE_1_S1DSS_BYPASS, + fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_nested_cdtable_ste(&s1_ste, + STRTAB_STE_1_S1DSS_BYPASS, + fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -601,6 +660,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0