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Tue, 27 Jan 2026 10:55:05 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v11 1/8] iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update Date: Tue, 27 Jan 2026 10:54:53 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|DS0PR12MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: b27217ed-c5fe-46b9-a065-08de5dd5a36a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nZa0rxUQkbAuYW41usjiGWQOBBGnryjZelNUAVTBCY2897fVUAIu1zBSSsZq?= =?us-ascii?Q?ZUrc5WN/7aRpRhvZNMwiPIiLLqAeV3URmT8FvohxXJDUr7oMdmtbaD+vr9VK?= =?us-ascii?Q?nragH7Zaz/BrcOAonCBw/rctPD5s+npqBmZY0CZ6EHhrnqmxh+pLPxtv2zkA?= =?us-ascii?Q?9uFpiJM8HIF4oDEe8QRsr8v1Ixp0k171Mq1Nkhkne10SCOq0+dT+jHRdj0Ei?= =?us-ascii?Q?jgIBg5XWqRftB1x7eDa727amv2llVls4qAF4S/8zoI4q829FrA7UJRPSwZ8Q?= =?us-ascii?Q?yAH8Zg1QHkHr9ZvzNrp2bZEr5JNSBehfaKLmH4bI/dLE+BL475EyZdS1OJyn?= =?us-ascii?Q?c6ny9VSYxI4MKTCrgmn7KuJBnearai6l1viszZx06v4GU+ocxC+uQUPkvL9R?= =?us-ascii?Q?kxckWW8ApV46l7pAUKICFcKvu67b5HgI/NyyYYcP8cq0OUL2EaH2Phg/82TS?= =?us-ascii?Q?uVGQamzd7q9FFwSCEKzwjssGy93yOFLWlHCD9ldhHioJSJQy9U/6pLBluANn?= =?us-ascii?Q?Z9wPBff90nSuwhbIMcDWBhs62EfxporeN7VxQaeCXGvJSv3g2uOyWXoM6Mo8?= =?us-ascii?Q?aH3/a3XumfrV2PSgtVZMZTrKlAznS1hVbNLnKOWm3HI4P5npLbTryo3rLhQt?= =?us-ascii?Q?FUFNWkcSewGVRRNyZmhQnhN+au2M0r7hmRWH1dWnW0x0cSC6DqyjueWOjYmx?= =?us-ascii?Q?26syJWzr95Ujt1tSl1FEA0vFyzubiFIxs0IA/kLXVquVa+Ywie6yHtm8s3vF?= =?us-ascii?Q?8/0P/GDzKjikvBYXWwgLqLNbG95MB6iQvxKyCJZFOQbGt5J1PDFnblyvwINy?= =?us-ascii?Q?KK25f2GlKD/yhzslQxDm3PT3fGO6gGn3rQtxxyQCugW7WXp+h08AzCIrX7dP?= =?us-ascii?Q?0mrF5vMzVXbWtnkw7sJtrMhUdE7QpMwv/jPXGMaWI4dTsPAN7JrU8r2Ggxhx?= =?us-ascii?Q?git3c9hCE4o85fnCbuEtPJZV/8L91BzDpl1qXOrrpo782Dns9ca1vPZUm21Z?= =?us-ascii?Q?jHD5eIG2lMNxhBkwf2gxKDKmnxHedRxmVMDjMhMr4rO70IiNq4AaI66QLBJw?= =?us-ascii?Q?jAC6FFMEHu8VMQH9sTRKsCfzgMmWDLsHNoymMgSaMztSW5rlQIvk/xQZVDjm?= =?us-ascii?Q?pe8IKkNU6djAI4ON4t3DW5kPPKqBnin9uXSkwj2AuR46S+M1d7f0KAcxZtKG?= =?us-ascii?Q?l/06H1z283ntR1iGt2rtlLxyZcaIjym15ZhTPtTUeh0nhXQ9NilEslYbsuUt?= =?us-ascii?Q?WE2/hs6eOEj3pr45RGIr0C/R8ulWkoUIbCcPDiCvzpVSm51ovAPQIiuG5hio?= =?us-ascii?Q?CVre0IcEhEwnNsOY3J0tNmbiSlUMpz0Z0TOM3ci1hW6zEqfkxTJR5sNW9NT9?= =?us-ascii?Q?T+65bGQUGoIUfVyHstM07R2vRu5WGfsLn1xVsc/nKDnnarle2Q3+/YZsJa8s?= =?us-ascii?Q?wcj2MVi5eEED5bBP541FO+PquKhD+/UWWGeeUDcjYuvVjv47boCBoyt6oQBS?= =?us-ascii?Q?VFs3NA1XYu6gh3Csr3Lr0dCsUJOCqHDPHuw3D4Ckxu3Rc/bevQlsv7xj8E25?= =?us-ascii?Q?HUme733KulpteaX7WDnOKpCyJVbqKYbrNGpBAqragfrAJDO8EXhdu0a+MyIC?= =?us-ascii?Q?5t7pHi1SDLMS9PpfZHMVNZVy40ao7csN+M36VMFntkCep2aFHxhS+Srx5Ywc?= =?us-ascii?Q?w5tBwA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 18:55:28.2412 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b27217ed-c5fe-46b9-a065-08de5dd5a36a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7655 Content-Type: text/plain; charset="utf-8" When writing a new (previously invalid) valid IOPTE to a page table, then installing the page table into an STE hitlesslessly (e.g. in S2TTB field), there is a window before an STE invalidation, where the page-table may be accessed by SMMU but the new IOPTE is still siting in the CPU cache. This could occur when we allocate an iommu_domain and immediately install it hitlessly, while there would be no dma_wmb() for the page table memory prior to the earliest point of HW reading the STE. Fix it by adding a dma_wmb() prior to updating the STE. Fixes: 56e1a4cc2588 ("iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_= entry") Cc: stable@vger.kernel.org Reported-by: Will Deacon Closes: https://lore.kernel.org/linux-iommu/aXdlnLLFUBwjT0V5@willie-the-tru= ck/ Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 852379845359..f0e3b407c293 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1236,6 +1236,13 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writ= er *writer, __le64 *entry, __le64 unused_update[NUM_ENTRY_QWORDS]; u8 used_qword_diff; =20 + /* + * Many of the entry structures have pointers to other structures that + * need to have their updates be visible before any writes of the entry + * happen. + */ + dma_wmb(); + used_qword_diff =3D arm_smmu_entry_qword_diff(writer, entry, target, unused_update); if (hweight8(used_qword_diff) =3D=3D 1) { --=20 2.43.0