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Mon, 26 Jan 2026 19:09:33 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v10 1/8] iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update Date: Mon, 26 Jan 2026 19:09:12 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|DM4PR12MB6086:EE_ X-MS-Office365-Filtering-Correlation-Id: dfa9c70b-4199-438e-4f97-08de5d5183cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?lkFV7ovoHYJFhTK52A96KTWxGdonXlt87P2iNeyR5Ln5D/ZzyT3g1nQNFHGd?= =?us-ascii?Q?8MCzbFgLQqqsdXtJkxYZYfxMta7+IpyM4oQodvN0/liyJ9wErSPQZTkw+23Y?= =?us-ascii?Q?rMyf3a81A7HsnU0kiNswYWYssHSXEi5gOEuVrGYXOvs1dNrTY7w5+9U0NCfq?= =?us-ascii?Q?PcCKfvtHdk+nlSCOIcgo0sJdTX27cjB+/PbKWbeEJgnnssCPOdySZsEhqsVZ?= =?us-ascii?Q?XcQDbh2hHk6JVGmSS0NBaa+cRf09feYXvKekwLFpxHcdPvjUgiYnLF1Hu+os?= =?us-ascii?Q?JeXpzD21CivvnH3y65JXZf+/CcrzRtgmz/gakrRcYzIjp2geyEWY339dTPPa?= =?us-ascii?Q?dhpFIjo8fkBEwU/II7Ms75Gy3MjFotfxBiwa14YPEWXATo/w6ofrnAczzU0N?= =?us-ascii?Q?TIb9MeH20CtRi1acQeV2faFf3VXY9jw3ubmFx2FHBkNPiPn+SvyqfyDBTTOY?= =?us-ascii?Q?VENdXityEW2yLmbaUDCH/C4XpCK7jelcH3MbpOd5SOkhs8IH6bvVAuyHU14Y?= =?us-ascii?Q?ag2oh4zvs5R0Pg3W2miELctvkuapnYvc+k32KKxH3COncA2xcq2bW5JK7F0A?= =?us-ascii?Q?JG/vyoSkHd02DqPAEKDCTUR3VvVhWXLUqGjYI+CU4fi3JS3KuGOBH7RcD+nd?= =?us-ascii?Q?eDVA9O5o/uw0xM9wzaTIwcqmtE7BGnnArfWoHCWFsh488ZQbbmDLlo4JXGq7?= =?us-ascii?Q?hlMro+MFbLM/nByxHyUBFQJO5ZcvcidtcChC0Bwnd2ttqyp7iqfP2NKfUljC?= =?us-ascii?Q?uZmAdrpFDeW6BQHIYtiv1y91b0Z+3qkNPLrDn7rWNHs8DcuiMPKyo87knnMg?= =?us-ascii?Q?lZjTpWdlSzzx9ZEZHKjUSbgHmLExkLJPOEr2BfxXSivLXokWJz0uqLxewMc5?= =?us-ascii?Q?z/nsicrb/VUoWvpAiUvc7R1QPG5B3KAytFuuq+e9ASKheYN7uUT90t132HLM?= =?us-ascii?Q?QOOgv5eCvU/W0MURJAtlkG8hP9r3F2ToxssyesGCJWs170U2bNXConE0DQnm?= =?us-ascii?Q?CHp73Czs/j1J3uVJGbSJTJtW2EicqCkCGL/jqWtPTfTrMRhNMiT3dm598B5u?= =?us-ascii?Q?F1tDbFy+4XSw7XzvsSvMnVqiVxhjI5YV0+L6rMEf6REGsorDuk9T88WrL36I?= =?us-ascii?Q?kpzI5sDsqgXPgI7Bkg5yq3hrCEeHDmY5ZeQ/tUUTtbVqSyqk+BpyghzncXNh?= =?us-ascii?Q?5dTLvCOkv27dEfYnmzUuZm5WX+ZWCYyhKQo7XKQ8CCqCTxCyd2MKJZ47sw8l?= =?us-ascii?Q?bQeHUzDis54sj3JLTlGYnLg/m4tiT8WBsKi7Y3LsE5ogpJ3Uh6TYNzKaOkPr?= =?us-ascii?Q?P6hlim1hslwwgbHcwlQuwCrsyjZHdPIOzKeUVzfKZuaeUHFVjzZxdVOt6sLr?= =?us-ascii?Q?zE/p+tDlBU66HqeHohV/UoaE3Na+mYkS0SdOKc0xSbJBk2KM6wtuehX5+diW?= =?us-ascii?Q?fEX+MipkaBLI4usJgBtp91vTVE7HnYj3AYMaH8BpcQgltN4lfzknwNveIAeI?= =?us-ascii?Q?S2ida5TAkL/GW08dKP4pT8PJbRYEDPjrZcIzSEmK0h/gG+sL8N8u6IO5BUUX?= =?us-ascii?Q?4oBBAyPlKMA4X7JqCH7mBCplfmxib07nH3lN+Nrl4x5BerZLO3RDOvHlsLaV?= =?us-ascii?Q?r5hxMbfpeNw5O6Kma2rJF4pMGtotc0rC9ULdNXfb4vqJwjFsB9x/lY5XOSVg?= =?us-ascii?Q?V57KWg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 03:09:41.6591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfa9c70b-4199-438e-4f97-08de5d5183cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6086 Content-Type: text/plain; charset="utf-8" When writing a new (previously invalid) valid IOPTE to a page table, then installing the page table into an STE hitlesslessly (e.g. in S2TTB field), there is a window before an STE invalidation, where the page-table may be accessed by SMMU but the new IOPTE is still siting in the CPU cache. This could occur when we allocate an iommu_domain and immediately install it hitlessly, while there would be no dma_wmb() for the page table memory prior to the earliest point of HW reading the STE. Fix it by adding a dma_wmb() prior to updating the STE. Fixes: 56e1a4cc2588 ("iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_= entry") Cc: stable@vger.kernel.org Reported-by: Will Deacon Closes: https://lore.kernel.org/linux-iommu/aXdlnLLFUBwjT0V5@willie-the-tru= ck/ Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 852379845359..f0e3b407c293 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1236,6 +1236,13 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writ= er *writer, __le64 *entry, __le64 unused_update[NUM_ENTRY_QWORDS]; u8 used_qword_diff; =20 + /* + * Many of the entry structures have pointers to other structures that + * need to have their updates be visible before any writes of the entry + * happen. + */ + dma_wmb(); + used_qword_diff =3D arm_smmu_entry_qword_diff(writer, entry, target, unused_update); if (hweight8(used_qword_diff) =3D=3D 1) { --=20 2.43.0