From nobody Sun Dec 14 13:45:45 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8F55A267387; Mon, 1 Sep 2025 12:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729236; cv=none; b=iq8QTP6PQMAIDsV3gyiOb+lKLXL2nRqoWhcUQj3TxaoCawJ+IH/SKo7TSoerz33lyLrco63pDe0E4TimVxG/4JXk99+qgJCYTSGStFW18qNftZ4db5sW0dkoogl8IEHmVkcMCSoqpDDGangEIyKvt4Vh/qoJ1thfusCQF3CZOew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729236; c=relaxed/simple; bh=6GGB8fj116M7fld93yabp+Sk9w91NwwwbI5I6K0AiZU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YmtHDAG0ZytzhNw5KUAFjRSE/KcbvA+ll8angr09NST/aXR2L4Onb4FIP4K7wTrNeNCfJTwLoU9gkZ+Zm+62aGnM9ZMvqo/Ppg4V3bQslnGiL4FpuMSFJfVRC12mSuzkcgqcTTE1B8C8FU7sZMVPsWeHSXYkyv8qyTvggKQwEGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cFndJ2RLlz9sSp; Mon, 1 Sep 2025 14:05:40 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Uqek8JJfWF8y; Mon, 1 Sep 2025 14:05:40 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cFndC5GNSz9sSq; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id A3ED18B790; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id UrGKXVX00Xao; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 7B3FA8B78C; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v5 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Mon, 1 Sep 2025 14:05:12 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=2384; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=6GGB8fj116M7fld93yabp+Sk9w91NwwwbI5I6K0AiZU=; b=jR+31eCAFRr4bN9Eu6xmfDeciVfmvlPu9ExV5VARP8nsAOGNFwb90XySqHjMyi1lIHHu36+2y LGi6cKMqC+ICyMni+CveDj7l2leszHXF7NXGxdBQNi1fciTurQMzy/U X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Signed-off-by: Christophe Leroy Acked-by: Conor Dooley --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 000000000000..a356ad8b13f5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy + +description: + Interrupt controller for the QUICC Engine I/O ports found on some Freesc= ale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + maxItems: 1 + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible =3D "fsl,mpc8323-qe-ports-ic"; + reg =3D <0xc00 0x18>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; + }; --=20 2.49.0