From nobody Mon Apr 13 15:44:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6792C4332F for ; Tue, 22 Nov 2022 07:40:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232492AbiKVHkk (ORCPT ); Tue, 22 Nov 2022 02:40:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232448AbiKVHk2 (ORCPT ); Tue, 22 Nov 2022 02:40:28 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 093FC17589 for ; Mon, 21 Nov 2022 23:39:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uGSJ7DPtFsorciAkWhHmN4hRW1hAr3Y9mVSmMvM8cgs=; b=OXwjCA8EU08bfMp/IWSWlK4upsCRm/k6RIu1R08bvQCjppyapAmg+AoGCCIQ9/NEnJSruj IGqHtaieGnHWi+HRge5KmC84vPfNPlPxL8F1ehyAUTxhxhA8n9IbNeiq6s1MTKSFKRQfRV lksnnx3ozgi960jJK2Nc78YOFSKUo/fRMossnVAXB8QuZhS266tUBBsWL+CzhG+e2D92sl Xvk4wiAl8SFJB5kuaZDrp2g71JsPO7serhn4wO4CGZKAeP6MwJ43zvU9uaV7xJY73fFZwf ROYSsj3iKVRHgqZDANMVmajNkJ3WdE+FvSWtuetAySH1sFRry9skWMvH/tjeyQ== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-564-hiVtk4evPvGvvH9_C1TAOw-1; Tue, 22 Nov 2022 02:39:24 -0500 X-MC-Unique: hiVtk4evPvGvvH9_C1TAOw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:20 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 2/4] x86/of: Introduce new optional bool property for lapic Date: Tue, 22 Nov 2022 15:39:08 +0800 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml index d4b99bf7bf6e..087f849e31ef 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 =20 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mod= e. + For ACPI or MPS spec compliant systems, it is figured out by some re= ad + only bit field/s available in their respective defined data structur= es. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt del= ivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible =3D "intel,ce4100-lapic"; reg =3D <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; --=20 2.17.1