From nobody Thu Oct 2 10:50:27 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C53682505AA; Thu, 18 Sep 2025 16:50:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214259; cv=none; b=TF5WtBbkubR9OUAk2pLqtVUdq+MspheBGe2CmWofYNjWXnmRU6sf16Sn/jDKfLKDeDGb5yrzDkDmPd90dQFxDy1/kZHhB4YZXzLrSTghce5RSCJacQ67o/qsrGgKu7zSUEusoHgJNRltiYfB8huZ4hEnDQ98dKvAzMDDMxPLlK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214259; c=relaxed/simple; bh=JPKAv81IjiGNw3TMzw+WVRovmT/FOWbfetWem9cmBzI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E7wcOjkqtaxPrrP0sGkt0Y/KZKeIO2+0HBvuk3QjuH8RCq9+/nQtzufdGzbcwIfBzYNcKPB47ovV2xe62d1X2AdkzdBMOLov9KMGFt1fT2CnlvNwm8iVUtn46CE0lKy8vISL+C/9TZKWkO6xoyi35roYw2/XCYWjFM9njpuBHOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cSLY33Jfxz9sfr; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id U-SAwV3r0x5Y; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cSLY249Jdz9sfj; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 7E49F8B767; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id pGYRopBfxKG1; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id BBF8E8B778; Thu, 18 Sep 2025 18:23:33 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver Date: Thu, 18 Sep 2025 18:23:22 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=4799; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=JPKAv81IjiGNw3TMzw+WVRovmT/FOWbfetWem9cmBzI=; b=9qbHdo/P81nMONTzCCSudErSniguq5Eb0y1BmQthiMKsaulHldEoExoiWx59usw/R3X7sDvgV mWeQfQrbtI0BRJXNaXw2Tw2/sa8eumjtQasowcu8pCmIwSkJuFC/ou1 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to be able to add interrupts to the GPIOs, first change the QE GPIO driver to the proper platform driver in order to allow initialisation to be done in the right order, otherwise the GPIOs get added before the interrupts are registered. Remove linux/of.h and linux/property.h which are unused. And to improve readability and reduce risk of errors, add a macro to transform a pin number into the mask that matches the associated bit in registers. Reviewed-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/gpio.c | 98 +++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 45 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 8df1e8fa86a5..04b44fc2bb58 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,16 +12,17 @@ #include #include #include -#include #include #include #include #include #include -#include +#include =20 #include =20 +#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio))) + struct qe_gpio_chip { struct of_mm_gpio_chip mm_gc; spinlock_t lock; @@ -52,7 +53,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) { struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); } @@ -63,7 +64,7 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; unsigned long flags; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 @@ -95,9 +96,9 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, break; if (__test_and_clear_bit(i, mask)) { if (test_bit(i, bits)) - qe_gc->cpdata |=3D (1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata |=3D PIN_MASK(i); else - qe_gc->cpdata &=3D ~(1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata &=3D ~PIN_MASK(i); } } =20 @@ -295,45 +296,52 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) } EXPORT_SYMBOL(qe_pin_set_gpio); =20 -static int __init qe_add_gpiochips(void) +static int qe_gpio_probe(struct platform_device *ofdev) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { - int ret; - struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; - struct gpio_chip *gc; - - qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); - if (!qe_gc) { - ret =3D -ENOMEM; - goto err; - } + struct device *dev =3D &ofdev->dev; + struct device_node *np =3D dev->of_node; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct gpio_chip *gc; =20 - spin_lock_init(&qe_gc->lock); - - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; - - mm_gc->save_regs =3D qe_gpio_save_regs; - gc->ngpio =3D QE_PIO_PINS; - gc->direction_input =3D qe_gpio_dir_in; - gc->direction_output =3D qe_gpio_dir_out; - gc->get =3D qe_gpio_get; - gc->set =3D qe_gpio_set; - gc->set_multiple =3D qe_gpio_set_multiple; - - ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); - if (ret) - goto err; - continue; -err: - pr_err("%pOF: registration failed with status %d\n", - np, ret); - kfree(qe_gc); - /* try others anyway */ - } - return 0; + qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) + return -ENOMEM; + + spin_lock_init(&qe_gc->lock); + + mm_gc =3D &qe_gc->mm_gc; + gc =3D &mm_gc->gc; + + mm_gc->save_regs =3D qe_gpio_save_regs; + gc->ngpio =3D QE_PIO_PINS; + gc->direction_input =3D qe_gpio_dir_in; + gc->direction_output =3D qe_gpio_dir_out; + gc->get =3D qe_gpio_get; + gc->set =3D qe_gpio_set; + gc->set_multiple =3D qe_gpio_set_multiple; + + return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); +} + +static const struct of_device_id qe_gpio_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, qe_gpio_match); + +static struct platform_driver qe_gpio_driver =3D { + .probe =3D qe_gpio_probe, + .driver =3D { + .name =3D "qe-gpio", + .of_match_table =3D qe_gpio_match, + }, +}; + +static int __init qe_gpio_init(void) +{ + return platform_driver_register(&qe_gpio_driver); } -arch_initcall(qe_add_gpiochips); +arch_initcall(qe_gpio_init); --=20 2.49.0