From nobody Tue Sep 16 02:25:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F9B5C54EBD for ; Sun, 8 Jan 2023 20:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233176AbjAHUAO (ORCPT ); Sun, 8 Jan 2023 15:00:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231378AbjAHT7w (ORCPT ); Sun, 8 Jan 2023 14:59:52 -0500 Received: from angie.orcam.me.uk (angie.orcam.me.uk [78.133.224.34]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AA048DBA for ; Sun, 8 Jan 2023 11:59:50 -0800 (PST) Received: by angie.orcam.me.uk (Postfix, from userid 500) id C996192009C; Sun, 8 Jan 2023 20:59:49 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id C290592009B; Sun, 8 Jan 2023 19:59:49 +0000 (GMT) Date: Sun, 8 Jan 2023 19:59:49 +0000 (GMT) From: "Maciej W. Rozycki" To: Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" cc: x86@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RESEND^3][PATCH v3] x86/PCI: Add support for the Intel 82378ZB/82379AB (SIO/SIO.A) PIRQ router Message-ID: User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel 82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)=20 ISA bridges implement PCI interrupt steering with a PIRQ router[1][2]=20 that is exactly the same as that of the PIIX and ICH southbridges (or=20 actually the other way round, given that the SIO ASIC was there first). An earlier version of the SIO, the 82378IB[3][4], does not implement PCI=20 interrupt steering however, so we need to exclude it by checking the low=20 nibble of the PCI Revision Identification Register[5][6] for being at=20 least 3. There is a note in the 82379AB specification update[7] saying that the=20 device ID for that chip is 0x7, rather than 0x484 as stated in the=20 datasheet[8]. It looks like a red herring however, for no report has=20 been ever seen with that value quoted and it matches the documented=20 default value of the PCI Command Register, which comes next after the=20 PCI Device Identification Register, so it looks like a copy-&-paste=20 editorial mistake. NB the 82378ZB has been commonly used with smaller DEC Alpha systems=20 with the contents of the Revision Identification Register reported as=20 one of 0x3, 0x43, or 0x84, so the masking of the high nibble seems=20 indeed right by empirical observation. The value in the high nibble=20 might be either random, or depend on the batch, or correspond to some=20 other state such as reset straps. References: [1] "82378 System I/O (SIO)", Intel Corporation, Order Number:=20 290473-004, December 1994, Section 4.1.26 "PIRQ[3:0]#--PIRQ Route=20 Control Registers" [2] "82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)", Intel Corporation, Order Number: 290571-001, March 1996, Section=20 3.1.25. "PIRQ[3:0]#--PIRQ Route Control Registers", p. 48 [3] "82378IB System I/O (SIO)", Intel Corporation, Order Number: 290473-002, April 1993, Section 5.8.7.7 "Edge and Level Triggered Modes" [4] "82378IB to 82378ZB Errata Fix and Feature Enhancement Conversion FOL933002-01", [5] "82378 System I/O (SIO)", Intel Corporation, Order Number:=20 290473-004, December 1994, Section 4.1.5. "RID--Revision=20 Identification Register" [6] "82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)", Intel Corporation, Order Number: 290571-001, March 1996, Section=20 3.1.5. "RID--Revision Identification Register", p. 34 [7] "Intel 82379AB (SIO.A) System I/O Component Specification Update",=20 Intel Corporation, Order Number: 297734-001, May, 1996, "Component=20 Identification via Programming Interface", p. 5 [8] "82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)", Intel Corporation, Order Number: 290571-001, March 1996, Section=20 3.1.2. "DID--Device Identification Register", p. 33 Signed-off-by: Maciej W. Rozycki --- Hi, This patch was dropped from x86/irq due to a bug in a follow-up patch and=20 when resent it was not re-picked up along with the other patches for some=20 reason. It applies unchanged to 6.2.0-rc3. Please apply. Maciej Changes from v2: - Regenerate for a merge conflict. Changes from v1: - Add [PATCH] annotation (umm...). - Fix RID values listed to include 0x84 rather than 0x83 (braino). --- arch/x86/pci/irq.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) linux-x86-pirq-router-sio.diff Index: linux-macro/arch/x86/pci/irq.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- linux-macro.orig/arch/x86/pci/irq.c +++ linux-macro/arch/x86/pci/irq.c @@ -974,11 +974,18 @@ static __init int intel_router_probe(str return 0; =20 switch (device) { + u8 rid; case PCI_DEVICE_ID_INTEL_82375: r->name =3D "PCEB/ESC"; r->get =3D pirq_esc_get; r->set =3D pirq_esc_set; return 1; + case PCI_DEVICE_ID_INTEL_82378: + pci_read_config_byte(router, PCI_REVISION_ID, &rid); + /* Tell 82378IB (rev < 3) and 82378ZB/82379AB apart. */ + if ((rid & 0xfu) < 3) + break; + fallthrough; case PCI_DEVICE_ID_INTEL_82371FB_0: case PCI_DEVICE_ID_INTEL_82371SB_0: case PCI_DEVICE_ID_INTEL_82371AB_0: @@ -1020,7 +1027,7 @@ static __init int intel_router_probe(str case PCI_DEVICE_ID_INTEL_ICH10_3: case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: - r->name =3D "PIIX/ICH"; + r->name =3D "SIO/PIIX/ICH"; r->get =3D pirq_piix_get; r->set =3D pirq_piix_set; return 1; @@ -1039,7 +1046,7 @@ static __init int intel_router_probe(str device <=3D PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) || (device >=3D PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device <=3D PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { - r->name =3D "PIIX/ICH"; + r->name =3D "SIO/PIIX/ICH"; r->get =3D pirq_piix_get; r->set =3D pirq_piix_set; return 1;