Hi all, Today's linux-next merge of the kvm tree got a conflict in: arch/x86/kvm/x86.c between commits: 3eaa50e1e255e ("x86/cpu: Hide and rename static_cpu_has()") 1620ddc0dcefc ("KVM/x86: Stop using 32-bit MSR interfaces") from the tip tree and commit: 7a26830801584 ("KVM: x86: Move the bulk of MSR specific code from x86.c to msrs.{c,h}") from the kvm tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c index XXXXXXX..XXXXXXX 100644 --- a/arch/x86/kvm/msrs.c +++ b/arch/x86/kvm/msrs.c @@ -XXX,XX +XXX,XX @@ static void kvm_probe_feature_msr(u32 msr_index) static void kvm_probe_msr_to_save(u32 msr_index) { - u32 dummy[2]; + u64 dummy; - if (rdmsr_safe(msr_index, &dummy[0], &dummy[1])) + if (rdmsrq_safe(msr_index, &dummy)) return; /* Hi all, Today's linux-next merge of the kvm tree got a conflict in: arch/x86/include/asm/sev-common.h between commit: 34ff659017359 ("x86/sev: Use kernel provided SVSM Calling Areas") from the tip tree and commit: d46b7b6a5f9ec ("KVM: SEV: Add support to handle MSR based Page State Change VMGEXIT") from the kvm tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. diff --cc arch/x86/include/asm/sev-common.h index e90d403f2068b,8647cc05e2f49..0000000000000 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@@ -98,19 -109,9 +109,22 @@@ enum psc_op /* GHCBData[63:32] */ \ (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) +/* GHCB Run at VMPL Request/Response */ +#define GHCB_MSR_VMPL_REQ 0x016 +#define GHCB_MSR_VMPL_REQ_LEVEL(v) \ + /* GHCBData[39:32] */ \ + (((u64)(v) & GENMASK_ULL(7, 0) << 32) | \ + /* GHCBDdata[11:0] */ \ + GHCB_MSR_VMPL_REQ) + +#define GHCB_MSR_VMPL_RESP 0x017 +#define GHCB_MSR_VMPL_RESP_VAL(v) \ + /* GHCBData[63:32] */ \ + (((u64)(v) & GENMASK_ULL(63, 32)) >> 32) + + /* Set highest bit as a generic error response */ + #define GHCB_MSR_PSC_RESP_ERROR (BIT_ULL(63) | GHCB_MSR_PSC_RESP) + /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081