From nobody Mon Feb 9 15:27:25 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABA4933B6D0 for ; Thu, 29 Jan 2026 10:16:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769681817; cv=none; b=gPyHiMaJR6ZuvNXKAz01hjw5ju/nsA+6KPrslBmjqON0sFyxGGKUQsMrzM7F/cYGuSrs7fVoTSCboG3gVY994BDXvJyi2msrmDUkFGGvs3ZW6JFGVAxshMoJ1moMe8YLkNjwQzuSHyp//Q9fGv6ZKfCetSNkE4NNoluuz16Olw0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769681817; c=relaxed/simple; bh=tiJxoBJKqiDxJyRh8KuDPOyTjxFZmwC+C2EPVKUwaD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZEkDClvN7i7ysVmy3arOn4SDoOw3F3hnFE0dv10JJhDuD7R/telMg/23iy+vFQP0J505V8LYvRDmT8vDw8j/f1mJ+Krwk5XWVn7KqJb5aSTogzjbpG9nD9+QWkRmBBuzzu6pxoSdhezdBh8a0cBw/ltaq5McxW+JA0zMaXr0Wgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VYQeChDY; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VYQeChDY" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-48069a48629so8241635e9.0 for ; Thu, 29 Jan 2026 02:16:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769681813; x=1770286613; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nayUkHKP6L91MLG9SEcHVEuSxFmIGO+/zRwcQEweek0=; b=VYQeChDYDveQvWyJARnWaHKoL4QekX02DOZeibrlahdaEF+WV/5Jo8Tw6HE+n8AQ8V 06svZuA1P/p366nYidXWtqfoxLOlq0cIoPO0USQWjHKjbuANxNHvhQSyF18XKZtq832e FLZaHynB3Thb7cmN8RKNcv0t7ezOQWkfpiXMp0UaOK4CdMqW7tSVo/LuorIA6hpiS4hp y03efKas2uCIQyvfPH2s9bLATN9p1QNk1zJTQcj2geYuMDrm4nxOT6b+emGC5aX+K/Lh iKHf8ewxMmtsdM8B0LIXEOZ5IoRhGY0NEEcZwtx9Wih/+u7IUAqgjCIdy0euBnJTHdT1 r2pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769681813; x=1770286613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=nayUkHKP6L91MLG9SEcHVEuSxFmIGO+/zRwcQEweek0=; b=A9Rvl8/61e3uxcSoG+cZYik0n4aZez4vw/Suconm/2QELxlcNCJ+UVrHyyX7yGZwS1 bkfGrxtT3KBaJxdDafXNDnNWifWzW9qQ8zdM2QVvr+Wxfj0v5VmxaBiCJF5v6XMW6mnb lpsPQaEiK2OvHsAHfjQkNCg00Lwht+yUphks1+Qp99Zv6MZZFHgrCCAP0IA0Zk8ehWCA xKDel+mouWfULx42O96fVTLqFTkL+hLAWK/ZtRFDu8xIawpaj0ojMF9ds2QXQwdBJK6z UnsNgljPXN/UXwqjLZlqkZxNLp1Z5XlNA/3tZjZEujoDiZLKVqC/h399WpjQkVxLx5j5 wdNQ== X-Forwarded-Encrypted: i=1; AJvYcCXTD9pyNSKu0kkf4kesKMqTktFcax2H4OtbD9Q1/x5k+05RTvqWOi/in2laxcZYSlx4+FkkGduphAuFX+E=@vger.kernel.org X-Gm-Message-State: AOJu0Yy3Fdopg2masCoKcAdln27ZLGNhkdw7h08KkkAAYRcaueKiZyqa n9GKp8SW0WTxSmbKSWbQRFwqQEvIwxBQoEVoJ3CkKeKjA007yoM1pELh X-Gm-Gg: AZuq6aKEijn+ByWfhzYeACbWBoujtHmJWQTWydmVQ7PcXiv5iSI74Ui7F5CIacgUA89 BEqpAC27fFmLhAhpIvnswfvJOLtOBgQLCw3YZuFWCUB2Hxx48knkMw/vFbAxAcc0u5JzFWxKrEi 5EcKfz1a2TCL7/ZRFDKj7MPEvO6SUNwtIiqaXSiZ1LQ5qscErNnem/4IxNTUm2MTDy9Me8zaLdw 1OV061W7nk3zMjHyNR22h+dbWKPHfssyDHtozfu/h+z/UuQhZZUErx4tpDOfLgRpUP9lC3H9nd+ EOUvNtJPdzKP/EayXV37QTOPteLYW036GCzVglFAJSaOLi1L6lo/EHI4l6FYpBKCSjdnAV9YhTo koPlYddPZWkn/Nt4CA+MXidlIm5vIRaGI5sHIVurZV/X4bmBQmFHJwIeRhtAln6nd+kFBkE2RO0 All6XFgt8nRiASitxo X-Received: by 2002:a05:600c:3e16:b0:477:7b16:5fb1 with SMTP id 5b1f17b1804b1-48069c0fde8mr114181015e9.7.1769681813003; Thu, 29 Jan 2026 02:16:53 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm178642065e9.2.2026.01.29.02.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 02:16:52 -0800 (PST) From: Biju X-Google-Original-From: Biju To: biju.das.au@gmail.com Cc: linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND 4/9] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Date: Thu, 29 Jan 2026 10:16:39 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 +++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..cf7f9c2e37f8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -63,10 +63,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ =20 +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -146,6 +154,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -906,6 +915,12 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_re= gister_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + return OTHER_POC; + if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + return OTHER_POC; + if (caps & PIN_CFG_WDTOVF_N_POC) + return OTHER_POC; =20 return -EINVAL; } @@ -925,6 +940,13 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps return pwr_reg; =20 val =3D readb(pctrl->base + pwr_reg); + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D (val >> offs) & 0x1; + } + switch (val) { case PVDD_1800: return 1800; @@ -943,6 +965,7 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl = *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; int pwr_reg; + u8 poc_val; u8 val; =20 if (caps & PIN_CFG_SOFT_PS) { @@ -952,15 +975,15 @@ static int rzg2l_set_power_source(struct rzg2l_pinctr= l *pctrl, u32 pin, u32 caps =20 switch (ps) { case 1800: - val =3D PVDD_1800; + poc_val =3D PVDD_1800; break; case 2500: if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) return -EINVAL; - val =3D PVDD_2500; + poc_val =3D PVDD_2500; break; case 3300: - val =3D PVDD_3300; + poc_val =3D PVDD_3300; break; default: return -EINVAL; @@ -970,6 +993,17 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; =20 + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D readb(pctrl->base + pwr_reg); + val &=3D ~BIT(offs); + val |=3D (poc_val << offs); + } else { + val =3D poc_val; + } + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source =3D ps; =20 --=20 2.43.0