From nobody Fri Oct 3 20:30:03 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E6CDC3D984; Tue, 26 Aug 2025 08:50:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756198237; cv=none; b=U+f1fUM5rMm7vnrevd8lk0y4Bw92r3N4M5qOcciTPkaezo5N/LOo3MnPlRrIO8CKNwr0t8RGo6r5bQMwrHuJbbBvYKlEySezvykAwBVp1aL64oNvqQoflJyMR7usYG6/xNUUCyiwoUgDD9pCTWOREEHN9GTWMn1DgvPEa5vwzcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756198237; c=relaxed/simple; bh=pJ0dqW2GCGa4yWArNPjCeHoPWJICNpv8ipt0j7ASM1Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FOHEP5UyfJzA0HO5ZVkwWZGSLv7spbBzm91KTHiHSw99rkAMvBAs4JtAl+tNN/XoSDP/Y+Rd5h9hRVCbXCK1/4IjB20si0PxXdVoO5e/amiVpj2+lIpy274VnpDHMGBiVm24AwRtX16XdzfKMTp/YkvPapY6DR+PBjEj3NCv5KI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cB1Np0NmHz9sSd; Tue, 26 Aug 2025 10:41:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id voHHKrBq8-UN; Tue, 26 Aug 2025 10:41:45 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cB1Nn6L1xz9sSc; Tue, 26 Aug 2025 10:41:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id C0CCD8B764; Tue, 26 Aug 2025 10:41:40 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id j9M1S24KLE1q; Tue, 26 Aug 2025 10:41:40 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 2D0548B763; Tue, 26 Aug 2025 10:41:40 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Tue, 26 Aug 2025 10:41:29 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: <372550a2633586d2f98b077d3f520f3262ca0e2a.1756104334.git.christophe.leroy@csgroup.eu> References: <372550a2633586d2f98b077d3f520f3262ca0e2a.1756104334.git.christophe.leroy@csgroup.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756197697; l=2931; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=pJ0dqW2GCGa4yWArNPjCeHoPWJICNpv8ipt0j7ASM1Y=; b=qXBDjnSeeKD6zixq9hi51WNrEhQvT+wzLU+IvEBZpjXb3EHCSVzw/98Sy6Ghh9g5fyNRHzWIE JBWupobYaCsCVFuqPZds6FTJG7GVp+fHpUTHxKDVXYEvdxzDll2r4CZ X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs are IRQ capable. Similarly to commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO"), add IRQ support to QE GPIO. Add property 'fsl,qe-gpio-irq-mask' similar to 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { compatible =3D "fsl,mpc8323-qe-pario-bank"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; interrupt-parent =3D <&qepic>; gpio-controller; #gpio-cells =3D <2>; fsl,qe-gpio-irq-mask =3D <0x01400050>; }; Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- v4: Using device_property_read_u32() instead of of_property_read_u32() --- drivers/soc/fsl/qe/gpio.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 5bf073bbaac8..68bcd6048b1c 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,11 +12,13 @@ #include #include #include +#include #include #include #include #include #include +#include =20 #include =20 @@ -30,6 +32,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[32]; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -133,6 +137,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -293,6 +304,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + u32 mask; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -300,6 +312,14 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + if (!device_property_read_u32(dev, "fsl,qe-gpio-irq-mask", &mask)) { + int i, j; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & (1 << (31 - i))) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + gc =3D &qe_gc->gc; =20 gc->base =3D -1; @@ -309,6 +329,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; gc->parent =3D dev; gc->owner =3D THIS_MODULE; =20 --=20 2.49.0