From nobody Fri Dec 19 07:02:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABF04C77B75 for ; Mon, 8 May 2023 20:10:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234081AbjEHUKJ (ORCPT ); Mon, 8 May 2023 16:10:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234267AbjEHUJU (ORCPT ); Mon, 8 May 2023 16:09:20 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98DFB83D8; Mon, 8 May 2023 13:08:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683576510; x=1715112510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ccJ7ex3fYIuaj8/TVXqPLF+MfKcH1klXSYN6/oR20DY=; b=ayEz2u7zod4Xnv8329rBAPO42k5ZUePrgtG4YsI51m0V2FDnrRohIoBp Kv9FY9Fey66/rGBj33xiekxveexuFRUM5m0YyFDj2Zau4tvfP5Lek7he4 beldyIR89MDCc2UIny21EBsjxRfgmsXvmQV1CetZEwlbbskhOdAOVcE3X JGEvMxuONBtfMeCNCRPRAPwijOhwDhF0ev7W99Sbg+8eBCLoCZz3SnrtE h7GEpXJsRkKC+xdQMAoVpZ+dEaiObU/q3y+feHrqQKVrbwLSLYaNQBKur 4VRHt+IljV8mDFiDFbqvyYbpV/YgaVp+rXQuOVfGggccU4/2vI2WgRVA+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="348573752" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="348573752" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 13:08:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="788241722" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="788241722" Received: from sajmal-mobl1.amr.corp.intel.com (HELO tzanussi-mobl1.intel.com) ([10.212.74.4]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 13:08:08 -0700 From: Tom Zanussi To: herbert@gondor.apana.org.au, davem@davemloft.net, fenghua.yu@intel.com, vkoul@kernel.org Cc: dave.jiang@intel.com, tony.luck@intel.com, wajdi.k.feghali@intel.com, james.guilford@intel.com, kanchana.p.sridhar@intel.com, giovanni.cabiddu@intel.com, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v4 14/15] crypto: iaa - Add irq support for the crypto async interface Date: Mon, 8 May 2023 15:07:36 -0500 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The existing iaa crypto async support provides an implementation that satisfies the interface but does so in a synchronous manner - it fills and submits the IDXD descriptor and then waits for it to complete before returning. This isn't a problem at the moment, since all existing callers (e.g. zswap) wrap any asynchronous callees in a synchronous wrapper anyway. This change makes the iaa crypto async implementation truly asynchronous: it fills and submits the IDXD descriptor, then returns immediately with -EINPROGRESS. It also sets the descriptor's 'request completion irq' bit and sets up a callback with the IDXD driver which is called when the operation completes and the irq fires. The existing callers such as zswap use synchronous wrappers to deal with -EINPROGRESS and so work as expected without any changes. This mode can be enabled by writing 'async_irq' to the sync_mode iaa_crypto driver attribute: echo async_irq > /sys/bus/dsa/drivers/crypto/sync_mode Async mode without interrupts (caller must poll) can be enabled by writing 'async' to it: echo async > /sys/bus/dsa/drivers/crypto/sync_mode The default sync mode can be enabled by writing 'sync' to it: echo sync > /sys/bus/dsa/drivers/crypto/sync_mode Signed-off-by: Tom Zanussi --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 226 ++++++++++++++++++++- 1 file changed, 224 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index c82e002043bb..b1293400d466 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -117,6 +117,102 @@ static ssize_t verify_compress_store(struct device_dr= iver *driver, } static DRIVER_ATTR_RW(verify_compress); =20 +/* + * The iaa crypto driver supports three 'sync' methods determining how + * compressions and decompressions are performed: + * + * - sync: the compression or decompression completes before + * returning. This is the mode used by the async crypto + * interface when the sync mode is set to 'sync' and by + * the sync crypto interface regardless of setting. + * + * - async: the compression or decompression is submitted and returns + * immediately. Completion interrupts are not used so + * the caller is responsible for polling the descriptor + * for completion. This mode is applicable to only the + * async crypto interface and is ignored for anything + * else. + * + * - async_irq: the compression or decompression is submitted and + * returns immediately. Completion interrupts are + * enabled so the caller can wait for the completion and + * yield to other threads. When the compression or + * decompression completes, the completion is signaled + * and the caller awakened. This mode is applicable to + * only the async crypto interface and is ignored for + * anything else. + * + * These modes can be set using the iaa_crypto sync_mode driver + * attribute. + */ + +/* Use async mode */ +static bool async_mode; +/* Use interrupts */ +static bool use_irq; + +/** + * set_iaa_sync_mode - Set IAA sync mode + * @name: The name of the sync mode + * + * Make the IAA sync mode named @name the current sync mode used by + * compression/decompression. + */ + +static int set_iaa_sync_mode(const char *name) +{ + int ret =3D 0; + + if (sysfs_streq(name, "sync")) { + async_mode =3D false; + use_irq =3D false; + } else if (sysfs_streq(name, "async")) { + async_mode =3D true; + use_irq =3D false; + } else if (sysfs_streq(name, "async_irq")) { + async_mode =3D true; + use_irq =3D true; + } else { + ret =3D -EINVAL; + } + + return ret; +} + +static ssize_t sync_mode_show(struct device_driver *driver, char *buf) +{ + int ret =3D 0; + + if (!async_mode && !use_irq) + ret =3D sprintf(buf, "%s\n", "sync"); + else if (async_mode && !use_irq) + ret =3D sprintf(buf, "%s\n", "async"); + else if (async_mode && use_irq) + ret =3D sprintf(buf, "%s\n", "async_irq"); + + return ret; +} + +static ssize_t sync_mode_store(struct device_driver *driver, + const char *buf, size_t count) +{ + int ret =3D -EBUSY; + + mutex_lock(&iaa_devices_lock); + + if (iaa_crypto_enabled) + goto out; + + ret =3D set_iaa_sync_mode(buf); + if (ret =3D=3D 0) + ret =3D count; +out: + mutex_unlock(&iaa_devices_lock); + + return ret; +} +static DRIVER_ATTR_RW(sync_mode); + static struct iaa_compression_mode *iaa_compression_modes[IAA_COMP_MODES_M= AX]; static int active_compression_mode; =20 @@ -1073,6 +1169,73 @@ static inline int check_completion(struct device *de= v, return ret; } =20 +static int iaa_compress_verify(struct crypto_tfm *tfm, struct acomp_req *r= eq, + struct idxd_wq *wq, + dma_addr_t src_addr, unsigned int slen, + dma_addr_t dst_addr, unsigned int *dlen, + u32 compression_crc); + +static void iaa_desc_complete(struct idxd_desc *idxd_desc, + enum idxd_complete_type comp_type, + bool free_desc, void *__ctx, + u32 *status) +{ + struct crypto_ctx *ctx =3D __ctx; + struct idxd_device *idxd; + struct iaa_wq *iaa_wq; + struct pci_dev *pdev; + struct device *dev; + int ret, err =3D 0; + + iaa_wq =3D idxd_wq_private(idxd_desc->wq); + idxd =3D iaa_wq->iaa_device->idxd; + pdev =3D idxd->pdev; + dev =3D &pdev->dev; + + dev_dbg(dev, "%s: compression mode %s," + " ctx->src_addr %llx, ctx->dst_addr %llx\n", __func__, + iaa_wq->iaa_device->active_compression_mode->name, + ctx->src_addr, ctx->dst_addr); + + ret =3D check_completion(dev, idxd_desc->iax_completion, + ctx->compress, false); + if (ret) { + dev_dbg(dev, "%s: check_completion failed ret=3D%d\n", __func__, ret); + err =3D -EIO; + goto err; + } + + ctx->req->dlen =3D idxd_desc->iax_completion->output_size; + + if (ctx->compress && iaa_verify_compress) { + u32 compression_crc; + + compression_crc =3D idxd_desc->iax_completion->crc; + dma_sync_sg_for_device(dev, ctx->req->dst, 1, DMA_FROM_DEVICE); + dma_sync_sg_for_device(dev, ctx->req->src, 1, DMA_TO_DEVICE); + ret =3D iaa_compress_verify(ctx->tfm, ctx->req, iaa_wq->wq, ctx->src_add= r, + ctx->req->slen, ctx->dst_addr, &ctx->req->dlen, + compression_crc); + if (ret) { + dev_dbg(dev, "%s: compress verify failed ret=3D%d\n", __func__, ret); + err =3D -EIO; + } + } +err: + if (ctx->req->base.complete) + acomp_request_complete(ctx->req, err); + + dma_unmap_sg(dev, ctx->req->dst, sg_nents(ctx->req->dst), DMA_FROM_DEVICE= ); + dma_unmap_sg(dev, ctx->req->src, sg_nents(ctx->req->src), DMA_TO_DEVICE); + + if (ret !=3D 0) + dev_dbg(dev, "asynchronous compress failed ret=3D%d\n", ret); + + if (free_desc) + idxd_free_desc(idxd_desc->wq, idxd_desc); + iaa_wq_put(idxd_desc->wq); +} + static int iaa_compress(struct crypto_tfm *tfm, struct acomp_req *req, struct idxd_wq *wq, dma_addr_t src_addr, unsigned int slen, @@ -1118,6 +1281,22 @@ static int iaa_compress(struct crypto_tfm *tfm, stru= ct acomp_req *req, desc->src2_size =3D sizeof(struct aecs_comp_table_record); desc->completion_addr =3D idxd_desc->compl_dma; =20 + if (use_irq) { + desc->flags |=3D IDXD_OP_FLAG_RCI; + + idxd_desc->crypto.req =3D req; + idxd_desc->crypto.tfm =3D tfm; + idxd_desc->crypto.src_addr =3D src_addr; + idxd_desc->crypto.dst_addr =3D dst_addr; + idxd_desc->crypto.compress =3D true; + + dev_dbg(dev, "%s use_async_irq: compression mode %s," + " src_addr %llx, dst_addr %llx\n", __func__, + iaa_wq->iaa_device->active_compression_mode->name, + src_addr, dst_addr); + } else if (async_mode && !disable_async) + req->base.data =3D idxd_desc; + dev_dbg(dev, "%s: compression mode %s," " desc->src1_addr %llx, desc->src1_size %d," " desc->dst_addr %llx, desc->max_dst_size %d," @@ -1132,6 +1311,12 @@ static int iaa_compress(struct crypto_tfm *tfm, stru= ct acomp_req *req, goto err; } =20 + if (async_mode && !disable_async) { + ret =3D -EINPROGRESS; + dev_dbg(dev, "%s: returning -EINPROGRESS\n", __func__); + goto out; + } + ret =3D check_completion(dev, idxd_desc->iax_completion, true, false); if (ret) { dev_dbg(dev, "check_completion failed ret=3D%d\n", ret); @@ -1142,7 +1327,8 @@ static int iaa_compress(struct crypto_tfm *tfm, struc= t acomp_req *req, =20 *compression_crc =3D idxd_desc->iax_completion->crc; =20 - idxd_free_desc(wq, idxd_desc); + if (!async_mode) + idxd_free_desc(wq, idxd_desc); out: return ret; err: @@ -1295,6 +1481,22 @@ static int iaa_decompress(struct crypto_tfm *tfm, st= ruct acomp_req *req, desc->flags |=3D IDXD_OP_FLAG_RD_SRC2_AECS; } =20 + if (use_irq && !disable_async) { + desc->flags |=3D IDXD_OP_FLAG_RCI; + + idxd_desc->crypto.req =3D req; + idxd_desc->crypto.tfm =3D tfm; + idxd_desc->crypto.src_addr =3D src_addr; + idxd_desc->crypto.dst_addr =3D dst_addr; + idxd_desc->crypto.compress =3D false; + + dev_dbg(dev, "%s: use_async_irq compression mode %s," + " src_addr %llx, dst_addr %llx\n", __func__, + iaa_wq->iaa_device->active_compression_mode->name, + src_addr, dst_addr); + } else if (async_mode && !disable_async) + req->base.data =3D idxd_desc; + dev_dbg(dev, "%s: decompression mode %s," " desc->src1_addr %llx, desc->src1_size %d," " desc->dst_addr %llx, desc->max_dst_size %d," @@ -1309,6 +1511,12 @@ static int iaa_decompress(struct crypto_tfm *tfm, st= ruct acomp_req *req, goto err; } =20 + if (async_mode && !disable_async) { + ret =3D -EINPROGRESS; + dev_dbg(dev, "%s: returning -EINPROGRESS\n", __func__); + goto out; + } + ret =3D check_completion(dev, idxd_desc->iax_completion, false, false); if (ret) { dev_dbg(dev, "check_completion failed ret=3D%d\n", ret); @@ -1317,7 +1525,8 @@ static int iaa_decompress(struct crypto_tfm *tfm, str= uct acomp_req *req, =20 *dlen =3D idxd_desc->iax_completion->output_size; =20 - idxd_free_desc(wq, idxd_desc); + if (!async_mode) + idxd_free_desc(wq, idxd_desc); out: return ret; err: @@ -1779,6 +1988,7 @@ static struct idxd_device_driver iaa_crypto_driver = =3D { .remove =3D iaa_crypto_remove, .name =3D IDXD_SUBDRIVER_NAME, .type =3D dev_types, + .desc_complete =3D iaa_desc_complete, }; =20 static int __init iaa_crypto_init_module(void) @@ -1821,10 +2031,20 @@ static int __init iaa_crypto_init_module(void) goto err_verify_attr_create; } =20 + ret =3D driver_create_file(&iaa_crypto_driver.drv, + &driver_attr_sync_mode); + if (ret) { + pr_debug("IAA sync mode attr creation failed\n"); + goto err_sync_attr_create; + } + pr_debug("initialized\n"); out: return ret; =20 +err_sync_attr_create: + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_verify_compress); err_verify_attr_create: driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_compression_mode); @@ -1843,6 +2063,8 @@ static void __exit iaa_crypto_cleanup_module(void) if (iaa_unregister_compression_device()) pr_debug("IAA compression device unregister failed\n"); =20 + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_sync_mode); driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_compression_mode); driver_remove_file(&iaa_crypto_driver.drv, --=20 2.34.1