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Mon, 14 Apr 2025 21:58:11 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 03/11] iommu/arm-smmu-v3: Share cmdq/cmd helpers with arm-smmu-v3-iommufd Date: Mon, 14 Apr 2025 21:57:38 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029927:EE_|DS5PPF482CFEB7D:EE_ X-MS-Office365-Filtering-Correlation-Id: 763af0f7-64d4-4e17-c72d-08dd7bda2839 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uVVtXMUNRnNPyKQoLJUk19CgAe6jTDMlbwWrF431H0aRe1aPK4coK/H5k34y?= =?us-ascii?Q?G12Jocu5Pxys/IhrLGvsVpLy3toVpSNBfL9VEq8wXVqFCkSF+YuYSVy0HcC4?= =?us-ascii?Q?UAHd3QkmYfsVum/8GyiE88EhOVwlGdtdQU0PrVeiMMyguSAN020S05tIpLar?= =?us-ascii?Q?llQDwKjTAiSwaID3QkRh3D606+pFhEFuyUYVUbSwhPgbFD/5EIhg8011AnS3?= =?us-ascii?Q?2H5VIzYcCmAK1+vtymtolCW0DKa7i/ouEkTcqpn86LVbc0dzCgXGaYyrJH6W?= =?us-ascii?Q?WMe/b0wXu+FrMYY7MKBhpoj0s0chFM5Htd2CHq5v6PPLKNLak630p7ICn0WQ?= =?us-ascii?Q?yWbbP9LlJt+GrMsACINJJgKhGl2KpNj+O1YEmoq3qXih7PLmvXoTLL2ErBN1?= =?us-ascii?Q?dD6PTUBgaj6dRyP4zwK1qygJnYkRQDA5lJ30KmC2SK7hOpg7N1e4Kkru0lGw?= =?us-ascii?Q?90XpFKDXaVAq9ERsXoFd8dV4FeKky2oiiUckdMdmHZfAj8lmQs9woLLHDl8E?= =?us-ascii?Q?nj9rfVS0KFlMm8+V5xhTln7Q0t7mKXg6BebJeTA/y2/8iOPnxSb6abw9w4BA?= =?us-ascii?Q?oERrM/nGsuOaqwjqkcCxfzWyKlLD9d7Tk4hcklrjMFLPIJsjzuzh0r7RncEE?= =?us-ascii?Q?aV3ueJVrRBN79l4s7J9XgQrP1kj6TiuVX4g4JJ8aP6i3LdGuwauV9YxWBPw2?= =?us-ascii?Q?IHAJqW9kG1WK6VAKFC1cdHj6sCB49/1isgDvZZDpFb9382DpZS1b054soh9f?= =?us-ascii?Q?+mq45ee4GFOxK5L+EsJsV5beM/znomQ+RFOpZgwoiA6MnsO1tf6HgctrAoEj?= =?us-ascii?Q?nTFhD7sJ1Qlc/OTNzLNPKuNJ3RQm5GrATuEw12oYbC6EbMZc550T9N/O5Q7x?= =?us-ascii?Q?K5htn4urcVUyY287+TLPh424Y+JufEcKvuuky9f6Kh5QK1P+WazdU9fzyccu?= =?us-ascii?Q?1JKb53Ne9n5DC3IzVAwDSnSqz1cp/aCDHvcecJP4qKYhs+2STzD6KKSNZQz3?= =?us-ascii?Q?TteZKHhpOXO96Iydg0rYQhXLM6BJ1RjDzNmu+/GhmQF1tFZ+sPBfOVpHxSpR?= =?us-ascii?Q?i2LBgBLCEW66QaAywqygK7Xmh6VrzEBLKMDDZAyb4MY4B/PVlNK3fa//IoNn?= =?us-ascii?Q?r4SW4RFbaQoG//0zh68KcnL9qZbl/lv0n/d3Cqp92xK8xCT1sagEexxa2HGd?= =?us-ascii?Q?Mw21bhRJrXMLh8EmrfUMPZlyx1wtEN57YbcvlquD0BtsuY7rAFBNhZEU8kEL?= =?us-ascii?Q?a6JVkcqFVwqby8l107kMgcApIKj0zXptKIhrdUT85KdI0LxDXfK89sH4NWxA?= =?us-ascii?Q?67l4dhf+tCwCQEfp/2pNP2rfvz4fJjaMax3VrGMO3KTMve89Lkv9Cem3GJJN?= =?us-ascii?Q?zOM9kjtgH/8Ki5lhocps1q1qcrDwrpx/kETupwEsVMi5b5Db94gJJSk0Nj8o?= =?us-ascii?Q?BwNRanC5YQsSpxNjc+VFhyw3yl2P+T34jXV0x6KCmFjeEckTgSXleCzI+FQn?= =?us-ascii?Q?kvhx/0AuVUsz6jMFYqBVW/OpJ0sgKL9v5zoW?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:26.2409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 763af0f7-64d4-4e17-c72d-08dd7bda2839 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029927.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF482CFEB7D Content-Type: text/plain; charset="utf-8" Allow arm-smmu-v3-iommufd to call them for nested/S2 cache invalidations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 ++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++++----------- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5dbdc61558a9..4f3f4a40a755 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -959,6 +959,8 @@ void __arm_smmu_tlb_inv_range(struct arm_smmu_device *s= mmu, struct arm_smmu_cmdq_ent *cmd, unsigned long iova, size_t size, size_t granule, struct iommu_domain *domain); +void arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, + struct arm_smmu_cmdq_ent *cmd); =20 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); @@ -996,6 +998,16 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_mast= er *master, int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, bool sync); +int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent); +void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *ent); +void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd); +int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds); =20 #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e9d4bbdacc99..8ad249f7dcbf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -929,23 +929,23 @@ static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_de= vice *smmu, return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); } =20 -static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_ent *ent) +int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent) { return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); } =20 -static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds, - struct arm_smmu_cmdq_ent *ent) +void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *ent) { cmds->num =3D 0; cmds->cmdq =3D arm_smmu_get_cmdq(smmu, ent); } =20 -static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds, - struct arm_smmu_cmdq_ent *cmd) +void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd) { bool unsupported_cmd =3D !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); bool force_sync =3D (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1) && @@ -974,8 +974,8 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_dev= ice *smmu, cmds->num++; } =20 -static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds) +int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds) { return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, cmds->num, true); @@ -2096,9 +2096,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int = irq, void *dev) return IRQ_WAKE_THREAD; } =20 -static void -arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, - struct arm_smmu_cmdq_ent *cmd) +void arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, + struct arm_smmu_cmdq_ent *cmd) { size_t log2_span; size_t span_mask; --=20 2.43.0