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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2025 10:52:24.6776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 112194ad-ab12-4714-67d7-08dd8d554053 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6098 Content-Type: text/plain; charset="utf-8" Current AMD IOMMU assumes Host Address Translation (HAT) is always supported, and Linux kernel enables this capability by default. However, in case of emulated and virtualized IOMMU, this might not be the case. For example,current QEMU-emulated AMD vIOMMU does not support host translation for VFIO pass-through device, but the interrupt remapping support is required for x2APIC (i.e. kvm-msi-ext-dest-id is also not supported by the guest OS). This would require the guest kernel to boot with guest kernel option iommu=3Dpt to by-pass the initialization of host (v1) table. The AMD I/O Virtualization Technology (IOMMU) Specification Rev 3.10 [1] introduces a new flag 'HATDis' in the IVHD 11h IOMMU attributes to indicate that HAT is not supported on a particular IOMMU instance. Therefore, modifies the AMD IOMMU driver to detect the new HATDis attributes, and disable host translation and switch to use guest translation if it is available. Otherwise, the driver will disable DMA translation. [1] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/sp= ecifications/48882_IOMMU.pdf Reviewed-by: Suravee Suthikulpanit Signed-off-by: Ankit Soni --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 6 +++++- drivers/iommu/amd/init.c | 21 ++++++++++++++++++++- drivers/iommu/amd/iommu.c | 13 +++++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 220c598b7e14..bb14c4800dd0 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -43,6 +43,7 @@ extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; extern unsigned long amd_iommu_pgsize_bitmap; +extern bool amd_iommu_hatdis; =20 /* Protection domain ops */ void amd_iommu_init_identity_domain(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5089b58e528a..284ff4309660 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -460,6 +460,9 @@ /* IOMMU Feature Reporting Field (for IVHD type 10h */ #define IOMMU_FEAT_GASUP_SHIFT 6 =20 +/* IOMMU HATDIS for IVHD type 11h and 40h */ +#define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0 + /* IOMMU Extended Feature Register (EFR) */ #define IOMMU_EFR_XTSUP_SHIFT 2 #define IOMMU_EFR_GASUP_SHIFT 7 @@ -558,7 +561,8 @@ struct amd_io_pgtable { }; =20 enum protection_domain_mode { - PD_MODE_V1 =3D 1, + PD_MODE_NONE, + PD_MODE_V1, PD_MODE_V2, }; =20 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 14aa0d77df26..cfda9f89fe1d 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -168,6 +168,9 @@ static int amd_iommu_target_ivhd_type; u64 amd_iommu_efr; u64 amd_iommu_efr2; =20 +/* Host (v1) page table is not supported*/ +bool amd_iommu_hatdis; + /* SNP is enabled on the system? */ bool amd_iommu_snp_en; EXPORT_SYMBOL(amd_iommu_snp_en); @@ -1798,6 +1801,11 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) amd_iommu_xt_mode =3D IRQ_REMAP_X2APIC_MODE; =20 + if (h->efr_attr & BIT(IOMMU_IVHD_ATTR_HATDIS_SHIFT)) { + pr_warn_once("Host Address Translation is not supported.\n"); + amd_iommu_hatdis =3D true; + } + early_iommu_features_init(iommu, h); =20 break; @@ -2582,7 +2590,7 @@ static void init_device_table_dma(struct amd_iommu_pc= i_seg *pci_seg) u32 devid; struct dev_table_entry *dev_table =3D pci_seg->dev_table; =20 - if (dev_table =3D=3D NULL) + if (!dev_table || amd_iommu_pgtable =3D=3D PD_MODE_NONE) return; =20 for (devid =3D 0; devid <=3D pci_seg->last_bdf; ++devid) { @@ -3095,6 +3103,17 @@ static int __init early_amd_iommu_init(void) } } =20 + if (amd_iommu_hatdis) { + /* + * Host (v1) page table is not available. Attempt to use + * Guest (v2) page table. + */ + if (amd_iommu_v2_pgtbl_supported()) + amd_iommu_pgtable =3D PD_MODE_V2; + else + amd_iommu_pgtable =3D PD_MODE_NONE; + } + /* Disable any previously enabled IOMMUs */ if (!is_kdump_kernel() || amd_iommu_disabled) disable_iommus(); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index f34209b08b4c..4e9a57377b8c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2393,6 +2393,13 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) pci_max_pasids(to_pci_dev(dev))); } =20 + if (amd_iommu_pgtable =3D=3D PD_MODE_NONE) { + pr_warn_once("%s: DMA translation not supported by iommu.\n", + __func__); + iommu_dev =3D ERR_PTR(-ENODEV); + goto out_err; + } + out_err: =20 iommu_completion_wait(iommu); @@ -2480,6 +2487,9 @@ static int pdom_setup_pgtable(struct protection_domai= n *domain, case PD_MODE_V2: fmt =3D AMD_IOMMU_V2; break; + case PD_MODE_NONE: + WARN_ON_ONCE(1); + return -EPERM; } =20 domain->iop.pgtbl.cfg.amd.nid =3D dev_to_node(dev); @@ -2501,6 +2511,9 @@ static inline u64 dma_max_address(enum protection_dom= ain_mode pgtable) =20 static bool amd_iommu_hd_support(struct amd_iommu *iommu) { + if (amd_iommu_hatdis) + return false; + return iommu && (iommu->features & FEATURE_HDSUP); } =20 --=20 2.43.0