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[188.152.100.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48523803b5fsm25167265e9.7.2026.03.06.11.58.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 11:58:50 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v2 11/11] arm64: dts: imx8mm-var-som-symphony: Enable PCIe Date: Fri, 6 Mar 2026 20:58:30 +0100 Message-ID: X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Enable PCIe support on the VAR-SOM Symphony carrier board by adding the external reference clock, configuring the PHY and providing the required clock and reset properties. Signed-off-by: Stefano Radaelli --- v1->v2: -=20 .../dts/freescale/imx8mm-var-som-symphony.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 9a29c81b06eb..0aa288af6c5e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -6,6 +6,7 @@ /dts-v1/; =20 #include +#include #include "imx8mm-var-som.dtsi" #include "imx8mm-var-som-wifi-bt-iw61x.dtsi" =20 @@ -17,6 +18,12 @@ chosen { stdout-path =3D &uart4; }; =20 + pcie0_refclk: pcie0-refclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; @@ -205,6 +212,27 @@ &i2c4 { status =3D "okay"; }; =20 +&pcie_phy { + fsl,refclk-pad-mode =3D ; + fsl,tx-deemph-gen1 =3D <0x2d>; + fsl,tx-deemph-gen2 =3D <0xf>; + fsl,clkreq-unsupported; + clocks =3D <&pcie0_refclk>; + status =3D "okay"; +}; + +&pcie0 { + reset-gpio =3D <&pca6408 1 GPIO_ACTIVE_LOW>; + clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates =3D <10000000>, <250000000>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status =3D "okay"; +}; + /* Header */ &uart1 { pinctrl-names =3D "default"; --=20 2.47.3