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[31.46.244.5]) by smtp.gmail.com with ESMTPSA id s9-20020a05640217c900b0053d9a862e2csm3598225edy.56.2023.10.12.11.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 11:12:04 -0700 (PDT) Sender: Ingo Molnar Date: Thu, 12 Oct 2023 20:12:02 +0200 From: Ingo Molnar To: Borislav Petkov Cc: linux-kernel@vger.kernel.org, linux-tip-commits@vger.kernel.org, rene@exactcode.de, x86@kernel.org, Peter Zijlstra Subject: [PATCH] x86/cpu: Fix the AMD Fam 17h, Fam 19h, Zen2 and Zen4 enumerations Message-ID: References: <169701622768.3135.17489375930381616520.tip-bot2@tip-bot2> <20231012074051.GBZSejA6bTV53638DE@fat_crate.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231012074051.GBZSejA6bTV53638DE@fat_crate.local> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" * Borislav Petkov wrote: > On Wed, Oct 11, 2023 at 11:28:26PM +0200, Ingo Molnar wrote: > > While in reality: > >=20 > > Zen 2 =3D=3D Fam 17h > > Zen 4 =3D=3D Fam 19h >=20 > If only were that easy... >=20 > family 0x17 is Zen1 and 2, family 0x19 is spread around Zen 3 and 4. > ... > See above. The MSRs are per Zen generation while the family is per > family. Yes, it is confusing. :-\ Fun! =20 > IOW, you want to have this as the end product: >=20 > /* Zen4 */ > #define MSR_ZEN4_BP_CFG 0xc001102e > #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 >=20 > /* Fam 19h MSRs */ > #define MSR_F19H_UMC_PERF_CTL 0xc0010800 > #define MSR_F19H_UMC_PERF_CTR 0xc0010801 >=20 > /* Zen 2 */ > #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 > #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) >=20 > /* Fam 17h MSRs */ > #define MSR_F17H_IRPERF 0xc00000e9 Ok, thanks - I've distilled your enumeration order into the separate patch below - there's more commits in perf/core meanwhile, and maybe it isn't even bad there's a bit of a spotlight on the naming scheme here. I've turned your above grouping & comments into a patch, created a=20 changelog and added your SOB, see the perf/core commit below. Lemme know if that's not OK to you. Thanks, Ingo =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D> From: Borislav Petkov Date: Thu, 12 Oct 2023 20:01:59 +0200 Subject: [PATCH] x86/cpu: Fix the AMD Fam 17h, Fam 19h, Zen2 and Zen4 MSR e= numerations The comments introduced in in the merge conflict fixup in: 8f4156d58713 ("Merge branch 'x86/urgent' into perf/core, to resolve confl= ict") ... aren't right: AMD naming schemes are more complex than implied, family 0x17 is Zen1 and 2, family 0x19 is spread around Zen 3 and 4. So there's indeed four separate MSR namespaces for: MSR_F17H_ MSR_F19H_ MSR_ZEN2_ MSR_ZEN4_ ... and the namespaces cannot be merged. Fix it up. No change in functionality. Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Ingo Molnar Cc: Peter Zijlstra Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactc= ode.com --- arch/x86/include/asm/msr-index.h | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 0ad9ba8baa8a..f8b502867dd1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -637,18 +637,20 @@ /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e =20 -/* Fam 19h (Zen 4) MSRs */ -#define MSR_F19H_UMC_PERF_CTL 0xc0010800 -#define MSR_F19H_UMC_PERF_CTR 0xc0010801 - -#define MSR_ZEN4_BP_CFG 0xc001102e +/* Zen4 */ +#define MSR_ZEN4_BP_CFG 0xc001102e #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 =20 -/* Fam 17h (Zen 2) MSRs */ -#define MSR_F17H_IRPERF 0xc00000e9 +/* Fam 19h MSRs */ +#define MSR_F19H_UMC_PERF_CTL 0xc0010800 +#define MSR_F19H_UMC_PERF_CTR 0xc0010801 =20 -#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 -#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) +/* Zen 2 */ +#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 +#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) + +/* Fam 17h MSRs */ +#define MSR_F17H_IRPERF 0xc00000e9 =20 /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL 0xc0010230