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Remove redundant type prefixes (e.g, `b`, `p`) in variable names, as explicit type encoding is not necessary in Linux kernel code which uses type definitions rather than variable name prefixes Suggested-by: Julia Lawall Signed-off-by: Abraham Samuel Adekunle --- .../staging/rtl8723bs/hal/HalPhyRf_8723B.c | 1184 ++++++++--------- drivers/staging/rtl8723bs/hal/odm.c | 462 +++---- .../staging/rtl8723bs/hal/odm_CfoTracking.c | 130 +- 3 files changed, 888 insertions(+), 888 deletions(-) diff --git a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c b/drivers/stagi= ng/rtl8723bs/hal/HalPhyRf_8723B.c index 81149ab81904..8b58f6c6d8f7 100644 --- a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c +++ b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c @@ -8,7 +8,7 @@ #include #include "odm_precomp.h" =20 -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */ +/* MACRO definition for rf_calibrate_info->TxIQC_8723B[0] */ #define PATH_S0 1 /* RF_PATH_B */ #define IDX_0xC94 0 #define IDX_0xC80 1 @@ -17,7 +17,7 @@ #define KEY 0 #define VAL 1 =20 -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */ +/* MACRO definition for rf_calibrate_info->TxIQC_8723B[1] */ #define PATH_S1 0 /* RF_PATH_A */ #define IDX_0xC4C 2 =20 @@ -41,7 +41,7 @@ static u8 DeltaSwingTableIdx_2GA_P_8188E[] =3D { =20 =20 static void setIqkMatrix_8723B( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, u8 OFDM_index, u8 RFPath, s32 IqkResult_X, @@ -73,26 +73,26 @@ static void setIqkMatrix_8723B( * element B is always 0 */ value32 =3D (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, valu= e32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value= 32); =20 value32 =3D (ele_C&0x000003C0)>>6; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); =20 value32 =3D ((IqkResult_X * ele_D)>>7)&0x01; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); break; case RF_PATH_B: /* write new elements A, C, D to regC88 and regC9C, * element B is always 0 */ value32 =3D (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, valu= e32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value= 32); =20 value32 =3D (ele_C&0x000003C0)>>6; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); =20 value32 =3D ((IqkResult_X * ele_D)>>7)&0x01; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); =20 break; default: @@ -101,15 +101,15 @@ static void setIqkMatrix_8723B( } else { switch (RFPath) { case RF_PATH_A: - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDM= SwingTable_New[OFDM_index]); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMS= wingTable_New[OFDM_index]); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); break; =20 case RF_PATH_B: - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDM= SwingTable_New[OFDM_index]); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMS= wingTable_New[OFDM_index]); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); break; =20 default: @@ -119,31 +119,31 @@ static void setIqkMatrix_8723B( } =20 =20 -static void setCCKFilterCoefficient(struct dm_odm_t *pDM_Odm, u8 CCKSwingI= ndex) +static void setCCKFilterCoefficient(struct dm_odm_t *dm_odm, u8 CCKSwingIn= dex) { - if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { - rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][0]); - rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][1]); - rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][2]); - rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][3]); - rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][4]); - rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][5]); - rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][6]); - rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingI= ndex][7]); + if (!dm_odm->RFCalibrateInfo.bCCKinCH14) { + rtw_write8(dm_odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][0]); + rtw_write8(dm_odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][1]); + rtw_write8(dm_odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][2]); + rtw_write8(dm_odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][3]); + rtw_write8(dm_odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][4]); + rtw_write8(dm_odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][5]); + rtw_write8(dm_odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][6]); + rtw_write8(dm_odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIn= dex][7]); } else { - rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex= ][0]); - rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex= ][1]); - rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex= ][2]); - rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex= ][3]); - rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex= ][4]); - rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex= ][5]); - rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex= ][6]); - rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex= ][7]); + rtw_write8(dm_odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex]= [0]); + rtw_write8(dm_odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex]= [1]); + rtw_write8(dm_odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex]= [2]); + rtw_write8(dm_odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex]= [3]); + rtw_write8(dm_odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex]= [4]); + rtw_write8(dm_odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex]= [5]); + rtw_write8(dm_odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex]= [6]); + rtw_write8(dm_odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex]= [7]); } } =20 void DoIQK_8723B( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, u8 DeltaThermalIndex, u8 ThermalValue, u8 Threshold @@ -169,14 +169,14 @@ void DoIQK_8723B( * *------------------------------------------------------------------------= ---*/ void ODM_TxPwrTrackSetPwr_8723B( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, enum pwrtrack_method Method, u8 RFPath, u8 ChannelMappedIndex ) { - struct adapter *Adapter =3D pDM_Odm->Adapter; - struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); + struct adapter *Adapter =3D dm_odm->Adapter; + struct hal_com_data *hal_data =3D GET_HAL_DATA(Adapter); u8 PwrTrackingLimit_OFDM =3D 34; /* 0dB */ u8 PwrTrackingLimit_CCK =3D 28; /* 2dB */ u8 TxRate =3D 0xFF; @@ -184,11 +184,11 @@ void ODM_TxPwrTrackSetPwr_8723B( u8 Final_CCK_Swing_Index =3D 0; =20 { - u16 rate =3D *(pDM_Odm->pForcedDataRate); + u16 rate =3D *(dm_odm->pForcedDataRate); =20 if (!rate) { /* auto rate */ - if (pDM_Odm->TxRate !=3D 0xFF) - TxRate =3D HwRateToMRate(pDM_Odm->TxRate); + if (dm_odm->TxRate !=3D 0xFF) + TxRate =3D HwRateToMRate(dm_odm->TxRate); } else /* force rate */ TxRate =3D (u8)rate; =20 @@ -213,23 +213,23 @@ void ODM_TxPwrTrackSetPwr_8723B( PwrTrackingLimit_OFDM =3D 34; /* 2dB */ =20 else - PwrTrackingLimit_OFDM =3D pDM_Odm->DefaultOfdmIndex; /* Default OFDM= index =3D 30 */ + PwrTrackingLimit_OFDM =3D dm_odm->DefaultOfdmIndex; /* Default OFDM = index =3D 30 */ } =20 if (Method =3D=3D TXAGC) { - struct adapter *Adapter =3D pDM_Odm->Adapter; + struct adapter *Adapter =3D dm_odm->Adapter; =20 - pDM_Odm->Remnant_OFDMSwingIdx[RFPath] =3D pDM_Odm->Absolute_OFDMSwingIdx= [RFPath]; + dm_odm->Remnant_OFDMSwingIdx[RFPath] =3D dm_odm->Absolute_OFDMSwingIdx[R= FPath]; =20 - pDM_Odm->Modify_TxAGC_Flag_PathA =3D true; - pDM_Odm->Modify_TxAGC_Flag_PathA_CCK =3D true; + dm_odm->Modify_TxAGC_Flag_PathA =3D true; + dm_odm->Modify_TxAGC_Flag_PathA_CCK =3D true; =20 - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChann= el, CCK); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChann= el, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChann= el, HT_MCS0_MCS7); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChann= el, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChann= el, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChann= el, HT_MCS0_MCS7); } else if (Method =3D=3D BBSWING) { - Final_OFDM_Swing_Index =3D pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute= _OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index =3D pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_O= FDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index =3D dm_odm->DefaultOfdmIndex + dm_odm->Absolute_O= FDMSwingIdx[RFPath]; + Final_CCK_Swing_Index =3D dm_odm->DefaultCckIndex + dm_odm->Absolute_OFD= MSwingIdx[RFPath]; =20 /* Adjust BB swing by OFDM IQ matrix */ if (Final_OFDM_Swing_Index >=3D PwrTrackingLimit_OFDM) @@ -239,69 +239,69 @@ void ODM_TxPwrTrackSetPwr_8723B( =20 if (Final_CCK_Swing_Index >=3D CCK_TABLE_SIZE) Final_CCK_Swing_Index =3D CCK_TABLE_SIZE-1; - else if (pDM_Odm->BbSwingIdxCck <=3D 0) + else if (dm_odm->BbSwingIdxCck <=3D 0) Final_CCK_Swing_Index =3D 0; =20 - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][0], - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][1]); + setIqkMatrix_8723B(dm_odm, Final_OFDM_Swing_Index, RFPath, + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInde= x][0], + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInde= x][1]); =20 - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + setCCKFilterCoefficient(dm_odm, Final_CCK_Swing_Index); =20 } else if (Method =3D=3D MIX_MODE) { - Final_OFDM_Swing_Index =3D pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute= _OFDMSwingIdx[RFPath]; - Final_CCK_Swing_Index =3D pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_O= FDMSwingIdx[RFPath]; + Final_OFDM_Swing_Index =3D dm_odm->DefaultOfdmIndex + dm_odm->Absolute_O= FDMSwingIdx[RFPath]; + Final_CCK_Swing_Index =3D dm_odm->DefaultCckIndex + dm_odm->Absolute_OFD= MSwingIdx[RFPath]; =20 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher = then Limit */ - pDM_Odm->Remnant_OFDMSwingIdx[RFPath] =3D Final_OFDM_Swing_Index - PwrT= rackingLimit_OFDM; + dm_odm->Remnant_OFDMSwingIdx[RFPath] =3D Final_OFDM_Swing_Index - PwrTr= ackingLimit_OFDM; =20 - setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][0], - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][1]); + setIqkMatrix_8723B(dm_odm, PwrTrackingLimit_OFDM, RFPath, + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][0], + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][1]); =20 - pDM_Odm->Modify_TxAGC_Flag_PathA =3D true; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, HT_MCS0_MCS7); + dm_odm->Modify_TxAGC_Flag_PathA =3D true; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, HT_MCS0_MCS7); } else if (Final_OFDM_Swing_Index <=3D 0) { - pDM_Odm->Remnant_OFDMSwingIdx[RFPath] =3D Final_OFDM_Swing_Index; + dm_odm->Remnant_OFDMSwingIdx[RFPath] =3D Final_OFDM_Swing_Index; =20 - setIqkMatrix_8723B(pDM_Odm, 0, RFPath, - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][0], - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][1]); + setIqkMatrix_8723B(dm_odm, 0, RFPath, + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][0], + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][1]); =20 - pDM_Odm->Modify_TxAGC_Flag_PathA =3D true; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, HT_MCS0_MCS7); + dm_odm->Modify_TxAGC_Flag_PathA =3D true; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, HT_MCS0_MCS7); } else { - setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][0], - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIn= dex][1]); - - if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset = TxAGC again */ - pDM_Odm->Remnant_OFDMSwingIdx[RFPath] =3D 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentCha= nnel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentCha= nnel, HT_MCS0_MCS7); - pDM_Odm->Modify_TxAGC_Flag_PathA =3D false; + setIqkMatrix_8723B(dm_odm, Final_OFDM_Swing_Index, RFPath, + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][0], + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedInd= ex][1]); + + if (dm_odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset T= xAGC again */ + dm_odm->Remnant_OFDMSwingIdx[RFPath] =3D 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentCha= nnel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentCha= nnel, HT_MCS0_MCS7); + dm_odm->Modify_TxAGC_Flag_PathA =3D false; } } =20 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { - pDM_Odm->Remnant_CCKSwingIdx =3D Final_CCK_Swing_Index - PwrTrackingLim= it_CCK; - setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); - pDM_Odm->Modify_TxAGC_Flag_PathA_CCK =3D true; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, CCK); + dm_odm->Remnant_CCKSwingIdx =3D Final_CCK_Swing_Index - PwrTrackingLimi= t_CCK; + setCCKFilterCoefficient(dm_odm, PwrTrackingLimit_CCK); + dm_odm->Modify_TxAGC_Flag_PathA_CCK =3D true; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, CCK); } else if (Final_CCK_Swing_Index <=3D 0) { /* Lowest CCK Index =3D 0 */ - pDM_Odm->Remnant_CCKSwingIdx =3D Final_CCK_Swing_Index; - setCCKFilterCoefficient(pDM_Odm, 0); - pDM_Odm->Modify_TxAGC_Flag_PathA_CCK =3D true; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChan= nel, CCK); + dm_odm->Remnant_CCKSwingIdx =3D Final_CCK_Swing_Index; + setCCKFilterCoefficient(dm_odm, 0); + dm_odm->Modify_TxAGC_Flag_PathA_CCK =3D true; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentChan= nel, CCK); } else { - setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); + setCCKFilterCoefficient(dm_odm, Final_CCK_Swing_Index); =20 - if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, re= set TxAGC again */ - pDM_Odm->Remnant_CCKSwingIdx =3D 0; - PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentCha= nnel, CCK); - pDM_Odm->Modify_TxAGC_Flag_PathA_CCK =3D false; + if (dm_odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, res= et TxAGC again */ + dm_odm->Remnant_CCKSwingIdx =3D 0; + PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, hal_data->CurrentCha= nnel, CCK); + dm_odm->Modify_TxAGC_Flag_PathA_CCK =3D false; } } } else @@ -309,30 +309,30 @@ void ODM_TxPwrTrackSetPwr_8723B( } =20 static void GetDeltaSwingTable_8723B( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, u8 **TemperatureUP_A, u8 **TemperatureDOWN_A, u8 **TemperatureUP_B, u8 **TemperatureDOWN_B ) { - struct adapter *Adapter =3D pDM_Odm->Adapter; - struct odm_rf_cal_t *pRFCalibrateInfo =3D &pDM_Odm->RFCalibrateInfo; - struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); - u16 rate =3D *(pDM_Odm->pForcedDataRate); - u8 channel =3D pHalData->CurrentChannel; + struct adapter *Adapter =3D dm_odm->Adapter; + struct odm_rf_cal_t *rf_calibrate_info =3D &dm_odm->RFCalibrateInfo; + struct hal_com_data *hal_data =3D GET_HAL_DATA(Adapter); + u16 rate =3D *(dm_odm->pForcedDataRate); + u8 channel =3D hal_data->CurrentChannel; =20 if (1 <=3D channel && channel <=3D 14) { if (IS_CCK_RATE(rate)) { - *TemperatureUP_A =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_A =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_B =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_B =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + *TemperatureUP_A =3D rf_calibrate_info->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A =3D rf_calibrate_info->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B =3D rf_calibrate_info->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B =3D rf_calibrate_info->DeltaSwingTableIdx_2GCCKB_N; } else { - *TemperatureUP_A =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B =3D pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + *TemperatureUP_A =3D rf_calibrate_info->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A =3D rf_calibrate_info->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B =3D rf_calibrate_info->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B =3D rf_calibrate_info->DeltaSwingTableIdx_2GB_N; } } else { *TemperatureUP_A =3D (u8 *)DeltaSwingTableIdx_2GA_P_8188E; @@ -343,19 +343,19 @@ static void GetDeltaSwingTable_8723B( } =20 =20 -void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *pConfig) +void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *config) { - pConfig->SwingTableSize_CCK =3D CCK_TABLE_SIZE; - pConfig->SwingTableSize_OFDM =3D OFDM_TABLE_SIZE; - pConfig->Threshold_IQK =3D IQK_THRESHOLD; - pConfig->AverageThermalNum =3D AVG_THERMAL_NUM_8723B; - pConfig->RfPathCount =3D MAX_PATH_NUM_8723B; - pConfig->ThermalRegAddr =3D RF_T_METER_8723B; - - pConfig->ODM_TxPwrTrackSetPwr =3D ODM_TxPwrTrackSetPwr_8723B; - pConfig->DoIQK =3D DoIQK_8723B; - pConfig->PHY_LCCalibrate =3D PHY_LCCalibrate_8723B; - pConfig->GetDeltaSwingTable =3D GetDeltaSwingTable_8723B; + config->SwingTableSize_CCK =3D CCK_TABLE_SIZE; + config->SwingTableSize_OFDM =3D OFDM_TABLE_SIZE; + config->Threshold_IQK =3D IQK_THRESHOLD; + config->AverageThermalNum =3D AVG_THERMAL_NUM_8723B; + config->RfPathCount =3D MAX_PATH_NUM_8723B; + config->ThermalRegAddr =3D RF_T_METER_8723B; + + config->ODM_TxPwrTrackSetPwr =3D ODM_TxPwrTrackSetPwr_8723B; + config->DoIQK =3D DoIQK_8723B; + config->PHY_LCCalibrate =3D PHY_LCCalibrate_8723B; + config->GetDeltaSwingTable =3D GetDeltaSwingTable_8723B; } =20 /* 1 7. IQK */ @@ -363,83 +363,83 @@ void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cf= g *pConfig) =20 /* bit0 =3D 1 =3D> Tx OK, bit1 =3D 1 =3D> Rx OK */ static u8 phy_PathA_IQK_8723B( - struct adapter *padapter, bool configPathB, u8 RF_Path + struct adapter *adapter, bool configPathB, u8 RF_Path ) { u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; u8 result =3D 0x00; =20 - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 /* Save RF Path */ - Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); + Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* enable path A PA in TXIQK mode */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0003f); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xc7f87); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0003f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= c7f87); /* disable path B PA in TXIQK mode */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00= 020); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40= ec1); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x000= 20); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40e= c1); */ =20 /* 1 Tx IQK */ /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); /* path-A IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); +/* PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */ + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* Ant switch */ if (configPathB || (RF_Path =3D=3D 0)) /* wifi switch to S1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000000); else /* wifi switch to S0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path A LOK & IQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 /* delay x ms */ /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regE94 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMask= DWord); - regE9C =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskD= Word); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regE94 =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK_A, bMaskD= Word); + regE9C =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_A, bMaskDW= ord); =20 =20 /* Allen 20131125 */ @@ -464,82 +464,82 @@ static u8 phy_PathA_IQK_8723B( =20 /* bit0 =3D 1 =3D> Tx OK, bit1 =3D 1 =3D> Rx OK */ static u8 phy_PathA_RxIQK8723B( - struct adapter *padapter, bool configPathB, u8 RF_Path + struct adapter *adapter, bool configPathB, u8 RF_Path ) { u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; u8 result =3D 0x00; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 /* Save RF Path */ - Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); + Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); /* 1 Get TXIMR setting */ /* modify RXIQK mode table */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); /* LNA2 off, PA on for Dcut */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xf7fb7); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= f7fb7); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); =20 /* path-A IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); =20 -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); +/* PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* Ant switch */ if (configPathB || (RF_Path =3D=3D 0)) /* wifi switch to S1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000000); else /* wifi switch to S0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path A LOK & IQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 /* delay x ms */ /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regE94 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMask= DWord); - regE9C =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskD= Word); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regE94 =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK_A, bMaskD= Word); + regE9C =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_A, bMaskDW= ord); =20 /* Allen 20131125 */ tmp =3D (regE9C & 0x03FF0000)>>16; @@ -559,78 +559,78 @@ static u8 phy_PathA_RxIQK8723B( return result; =20 u4tmp =3D 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); =20 /* modify RXIQK mode table */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); /* LAN2 on, PA off for Dcut */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xf7d77); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= f7d77); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ =20 /* PA, PAD setting */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f= ); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); =20 =20 /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); =20 /* path-A IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +/* PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* Ant switch */ if (configPathB || (RF_Path =3D=3D 0)) /* wifi switch to S1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000000); else /* wifi switch to S0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path A LOK & IQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 /* delay x ms */ /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regEA4 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMa= skDWord); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regEA4 =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_Before_IQK_A_2, bMas= kDWord); =20 /* PA/PAD controlled by 0x0 */ /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); =20 /* Allen 20131125 */ tmp =3D (regEAC & 0x03FF0000)>>16; @@ -651,79 +651,79 @@ static u8 phy_PathA_RxIQK8723B( } =20 /* bit0 =3D 1 =3D> Tx OK, bit1 =3D 1 =3D> Rx OK */ -static u8 phy_PathB_IQK_8723B(struct adapter *padapter) +static u8 phy_PathB_IQK_8723B(struct adapter *adapter) { u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_= BB*/; u8 result =3D 0x00; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 /* Save RF Path */ - Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); + Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* in TXIQK mode */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask,= 0x20000); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask= , 0x0003f); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask= , 0xc7f87); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, = 0x20000); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask,= 0x0003f); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask,= 0xc7f87); */ /* enable path B PA in TXIQK mode */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1= ); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1); =20 =20 =20 /* 1 Tx IQK */ /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); /* path-A IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); =20 -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); +/* PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */ + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* switch to path B */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xef= fe0); */ + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeff= e0); */ =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path B LOK & IQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 /* delay x ms */ /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regE94 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMask= DWord); - regE9C =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskD= Word); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regE94 =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK_A, bMaskD= Word); + regE9C =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_A, bMaskDW= ord); =20 /* Allen 20131125 */ tmp =3D (regE9C & 0x03FF0000)>>16; @@ -744,63 +744,63 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapte= r) } =20 /* bit0 =3D 1 =3D> Tx OK, bit1 =3D 1 =3D> Rx OK */ -static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB) +static u8 phy_PathB_RxIQK8723B(struct adapter *adapter, bool configPathB) { u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; u8 result =3D 0x00; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 /* Save RF Path */ - Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); + Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* switch to path B */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); /* modify RXIQK mode table */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xf7fb7); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= f7fb7); /* open PA S1 & SMIXER */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd= ); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd); =20 =20 /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); =20 =20 /* path-B IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); =20 -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); +/* PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* switch to path B */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xef= fe0); */ + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeff= e0); */ =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path B TXIQK @ RXIQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 =20 /* delay x ms */ @@ -808,17 +808,17 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapt= er, bool configPathB) mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regE94 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMask= DWord); - regE9C =3D PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskD= Word); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regE94 =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK_A, bMaskD= Word); + regE9C =3D PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_A, bMaskDW= ord); =20 /* Allen 20131125 */ tmp =3D (regE9C & 0x03FF0000)>>16; @@ -838,77 +838,77 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapt= er, bool configPathB) return result; =20 u4tmp =3D 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); =20 /* modify RXIQK mode table */ /* 20121009, Kordan> RF Mode =3D 3 */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xf7d77); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= f7d77); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ =20 /* open PA S1 & close SMIXER */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd= ); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd); =20 /* PA, PAD setting */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf8= 0); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51= 000); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80= ); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x510= 00); */ =20 /* IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); =20 /* path-B IQK setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); -/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); = */ - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); +/* PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); =20 /* LO calibration setting */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); =20 /* enter IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); =20 /* switch to path B */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xef= fe0); */ + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, 0x00000280); +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeff= e0); */ =20 /* GNT_BT =3D 0 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00000800); =20 /* One shot, path B LOK & IQK */ - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(dm_odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); =20 /* delay x ms */ /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ mdelay(IQK_DELAY_TIME_8723B); =20 /* restore Ant Path */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); + PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); /* GNT_BT =3D 1 */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, 0x00001800); =20 /* leave IQK mode */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); =20 /* Check failed */ - regEAC =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMas= kDWord); - regEA4 =3D PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMa= skDWord); + regEAC =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_A_2, bMask= DWord); + regEA4 =3D PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_Before_IQK_A_2, bMas= kDWord); =20 /* PA/PAD controlled by 0x0 */ /* leave IQK mode */ -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x18= 0); */ +/* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180= ); */ =20 =20 =20 @@ -931,33 +931,33 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapt= er, bool configPathB) } =20 static void _PHY_PathAFillIQKMatrix8723B( - struct adapter *padapter, - bool bIQKOK, + struct adapter *adapter, + bool iqkok, s32 result[][8], u8 final_candidate, - bool bTxOnly + bool tx_only ) { u32 Oldval_0, X, TX0_A, reg; s32 Y, TX0_C; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 - struct odm_rf_cal_t *pRFCalibrateInfo =3D &pDM_Odm->RFCalibrateInfo; + struct odm_rf_cal_t *rf_calibrate_info =3D &dm_odm->RFCalibrateInfo; =20 if (final_candidate =3D=3D 0xFF) return; =20 - else if (bIQKOK) { - Oldval_0 =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, b= MaskDWord) >> 22) & 0x3FF; + else if (iqkok) { + Oldval_0 =3D (PHY_QueryBBReg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, bM= askDWord) >> 22) & 0x3FF; =20 X =3D result[final_candidate][0]; if ((X & 0x00000200) !=3D 0) X =3D X | 0xFFFFFC00; TX0_A =3D (X * Oldval_0) >> 8; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval= _0>>7) & 0x1)); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_= 0>>7) & 0x1)); =20 Y =3D result[final_candidate][1]; if ((Y & 0x00000200) !=3D 0) @@ -965,74 +965,74 @@ static void _PHY_PathAFillIQKMatrix8723B( =20 /* 2 Tx IQC */ TX0_C =3D (Y * Oldval_0) >> 8; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0= )>>6)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] =3D rOFDM0_XCTxAF= E; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)= >>6)); + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] =3D rOFDM0_XCTxA= FE; + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_= C&0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] =3D rOFDM0_XATxIQ= Imbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C= &0x3F)); + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] =3D rOFDM0_XATxI= QImbalance; + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval= _0>>7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] =3D rOFDM0_ECCATh= reshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_= 0>>7) & 0x1)); + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] =3D rOFDM0_ECCAT= hreshold; + rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); =20 - if (bTxOnly) { + if (tx_only) { /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] =3D rOFDM0_RxIQE= xtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] =3D 0xfffffff & = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] =3D rOFDM0_XARxI= QImbalance; -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D PHY_Query= BBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D 0x40000100; + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] =3D rOFDM0_RxIQ= ExtAnta; + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] =3D 0xfffffff &= PHY_QueryBBReg(dm_odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] =3D rOFDM0_XARx= IQImbalance; +/* rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D PHY_Quer= yBBReg(dm_odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D 0x40000100; return; } =20 reg =3D result[final_candidate][2]; =20 /* 2 Rx IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); reg =3D result[final_candidate][3] & 0x3F; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] =3D rOFDM0_XARxIQ= Imbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] =3D rOFDM0_XARxI= QImbalance; + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); =20 reg =3D (result[final_candidate][3] >> 6) & 0xF; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] =3D rOFDM0_RxIQEx= tAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] =3D rOFDM0_RxIQE= xtAnta; + rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); =20 } } =20 static void _PHY_PathBFillIQKMatrix8723B( - struct adapter *padapter, - bool bIQKOK, + struct adapter *adapter, + bool iqkok, s32 result[][8], u8 final_candidate, - bool bTxOnly /* do Tx only */ + bool tx_only /* do Tx only */ ) { u32 Oldval_1, X, TX1_A, reg; s32 Y, TX1_C; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 - struct odm_rf_cal_t *pRFCalibrateInfo =3D &pDM_Odm->RFCalibrateInfo; + struct odm_rf_cal_t *rf_calibrate_info =3D &dm_odm->RFCalibrateInfo; =20 if (final_candidate =3D=3D 0xFF) return; =20 - else if (bIQKOK) { - Oldval_1 =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, b= MaskDWord) >> 22) & 0x3FF; + else if (iqkok) { + Oldval_1 =3D (PHY_QueryBBReg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, bM= askDWord) >> 22) & 0x3FF; =20 X =3D result[final_candidate][4]; if ((X & 0x00000200) !=3D 0) X =3D X | 0xFFFFFC00; TX1_A =3D (X * Oldval_1) >> 8; =20 - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); =20 - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval= _1>>7) & 0x1)); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_= 1>>7) & 0x1)); =20 Y =3D result[final_candidate][5]; if ((Y & 0x00000200) !=3D 0) @@ -1041,41 +1041,41 @@ static void _PHY_PathBFillIQKMatrix8723B( TX1_C =3D (Y * Oldval_1) >> 8; =20 /* 2 Tx IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0= )>>6)); -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] =3D rOFDM0_XDT= xAFE; */ -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] =3D PHY_QueryB= BReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */ - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] =3D rOFDM0_XCTxAF= E; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); - - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_= C&0x3F)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] =3D rOFDM0_XATxIQ= Imbalance; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord); - - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval= _1>>7) & 0x1)); - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] =3D rOFDM0_ECCATh= reshold; - pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); - - if (bTxOnly) { - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] =3D rOFDM0_XARxI= QImbalance; -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D PHY_Query= BBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D 0x40000100; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] =3D rOFDM0_RxIQE= xtAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] =3D 0x0fffffff &= PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)= >>6)); +/* rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] =3D rOFDM0_XD= TxAFE; */ +/* rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] =3D PHY_Query= BBReg(dm_odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */ + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] =3D rOFDM0_XCTxA= FE; + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); + + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C= &0x3F)); + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] =3D rOFDM0_XATxI= QImbalance; + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord); + + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_= 1>>7) & 0x1)); + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] =3D rOFDM0_ECCAT= hreshold; + rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); + + if (tx_only) { + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] =3D rOFDM0_XARx= IQImbalance; +/* rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D PHY_Quer= yBBReg(dm_odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D 0x40000100; + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] =3D rOFDM0_RxIQ= ExtAnta; + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] =3D 0x0fffffff = & PHY_QueryBBReg(dm_odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); return; } =20 /* 2 Rx IQC */ reg =3D result[final_candidate][6]; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); reg =3D result[final_candidate][7] & 0x3F; - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] =3D rOFDM0_XARxIQ= Imbalance; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D PHY_QueryBBRe= g(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] =3D rOFDM0_XARxI= QImbalance; + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] =3D PHY_QueryBBR= eg(dm_odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord); =20 reg =3D (result[final_candidate][7] >> 6) & 0xF; -/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);= */ - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] =3D rOFDM0_RxIQEx= tAnta; - pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] =3D (reg << 28)|(= PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff= ); +/* PHY_SetBBReg(dm_odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); = */ + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] =3D rOFDM0_RxIQE= xtAnta; + rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] =3D (reg << 28)|= (PHY_QueryBBReg(dm_odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff= ); } } =20 @@ -1084,33 +1084,33 @@ static void _PHY_PathBFillIQKMatrix8723B( /* */ /* MP Already declare in odm.c */ =20 -void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath) +void ODM_SetIQCbyRFpath(struct dm_odm_t *dm_odm, u32 RFpath) { =20 - struct odm_rf_cal_t *pRFCalibrateInfo =3D &pDM_Odm->RFCalibrateInfo; + struct odm_rf_cal_t *rf_calibrate_info =3D &dm_odm->RFCalibrateInfo; =20 if ( - (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] !=3D 0x0) && - (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] !=3D 0x0) && - (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] !=3D 0x0) && - (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] !=3D 0x0) + (rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] !=3D 0x0) && + (rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] !=3D 0x0) && + (rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] !=3D 0x0) && + (rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] !=3D 0x0) ) { if (RFpath) { /* S1: RFpath =3D 0, S0:RFpath =3D 1 */ /* S0 TX IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][I= DX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9= 4][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][I= DX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC8= 0][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][I= DX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4= C][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S0][I= DX_0xC94][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC= 94][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S0][I= DX_0xC80][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC= 80][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S0][I= DX_0xC4C][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S0][IDX_0xC= 4C][VAL]); /* S0 RX IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][I= DX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC1= 4][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][I= DX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA= 0][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->RxIQC_8723B[PATH_S0][I= DX_0xC14][KEY], bMaskDWord, rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC= 14][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->RxIQC_8723B[PATH_S0][I= DX_0xCA0][KEY], bMaskDWord, rf_calibrate_info->RxIQC_8723B[PATH_S0][IDX_0xC= A0][VAL]); } else { /* S1 TX IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][I= DX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC9= 4][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][I= DX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC8= 0][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][I= DX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4= C][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S1][I= DX_0xC94][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC= 94][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S1][I= DX_0xC80][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC= 80][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->TxIQC_8723B[PATH_S1][I= DX_0xC4C][KEY], bMaskDWord, rf_calibrate_info->TxIQC_8723B[PATH_S1][IDX_0xC= 4C][VAL]); /* S1 RX IQC */ - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][I= DX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC1= 4][VAL]); - PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][I= DX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA= 0][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->RxIQC_8723B[PATH_S1][I= DX_0xC14][KEY], bMaskDWord, rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC= 14][VAL]); + PHY_SetBBReg(dm_odm->Adapter, rf_calibrate_info->RxIQC_8723B[PATH_S1][I= DX_0xCA0][KEY], bMaskDWord, rf_calibrate_info->RxIQC_8723B[PATH_S1][IDX_0xC= A0][VAL]); } } } @@ -1121,114 +1121,114 @@ static bool ODM_CheckPowerStatus(struct adapter *= Adapter) } =20 static void _PHY_SaveADDARegisters8723B( - struct adapter *padapter, + struct adapter *adapter, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum ) { u32 i; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 - if (!ODM_CheckPowerStatus(padapter)) + if (!ODM_CheckPowerStatus(adapter)) return; =20 for (i =3D 0 ; i < RegisterNum ; i++) { - ADDABackup[i] =3D PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWor= d); + ADDABackup[i] =3D PHY_QueryBBReg(dm_odm->Adapter, ADDAReg[i], bMaskDWord= ); } } =20 =20 static void _PHY_SaveMACRegisters8723B( - struct adapter *padapter, u32 *MACReg, u32 *MACBackup + struct adapter *adapter, u32 *MACReg, u32 *MACBackup ) { u32 i; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 for (i =3D 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { - MACBackup[i] =3D rtw_read8(pDM_Odm->Adapter, MACReg[i]); + MACBackup[i] =3D rtw_read8(dm_odm->Adapter, MACReg[i]); } - MACBackup[i] =3D rtw_read32(pDM_Odm->Adapter, MACReg[i]); + MACBackup[i] =3D rtw_read32(dm_odm->Adapter, MACReg[i]); =20 } =20 =20 static void _PHY_ReloadADDARegisters8723B( - struct adapter *padapter, + struct adapter *adapter, u32 *ADDAReg, u32 *ADDABackup, u32 RegiesterNum ) { u32 i; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 for (i =3D 0 ; i < RegiesterNum; i++) { - PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]); + PHY_SetBBReg(dm_odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]); } } =20 static void _PHY_ReloadMACRegisters8723B( - struct adapter *padapter, u32 *MACReg, u32 *MACBackup + struct adapter *adapter, u32 *MACReg, u32 *MACBackup ) { u32 i; =20 for (i =3D 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { - rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]); + rtw_write8(adapter, MACReg[i], (u8)MACBackup[i]); } - rtw_write32(padapter, MACReg[i], MACBackup[i]); + rtw_write32(adapter, MACReg[i], MACBackup[i]); } =20 =20 static void _PHY_PathADDAOn8723B( - struct adapter *padapter, + struct adapter *adapter, u32 *ADDAReg, bool is2T ) { u32 pathOn; u32 i; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 pathOn =3D 0x01c00014; if (!is2T) { pathOn =3D 0x01c00014; - PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014); + PHY_SetBBReg(dm_odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014); } else { - PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn); + PHY_SetBBReg(dm_odm->Adapter, ADDAReg[0], bMaskDWord, pathOn); } =20 for (i =3D 1 ; i < IQK_ADDA_REG_NUM ; i++) { - PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn); + PHY_SetBBReg(dm_odm->Adapter, ADDAReg[i], bMaskDWord, pathOn); } =20 } =20 static void _PHY_MACSettingCalibration8723B( - struct adapter *padapter, u32 *MACReg, u32 *MACBackup + struct adapter *adapter, u32 *MACReg, u32 *MACBackup ) { u32 i =3D 0; - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 - rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F); + rtw_write8(dm_odm->Adapter, MACReg[i], 0x3F); =20 for (i =3D 1 ; i < (IQK_MAC_REG_NUM - 1); i++) { - rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); + rtw_write8(dm_odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); } - rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); + rtw_write8(dm_odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); =20 } =20 static bool phy_SimularityCompare_8723B( - struct adapter *padapter, + struct adapter *adapter, s32 result[][8], u8 c1, u8 c2 @@ -1311,20 +1311,20 @@ static bool phy_SimularityCompare_8723B( =20 =20 static void phy_IQCalibrate_8723B( - struct adapter *padapter, + struct adapter *adapter, s32 result[][8], u8 t, bool is2T, u8 RF_Path ) { - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 u32 i; u8 PathAOK, PathBOK; - u8 tmp0xc50 =3D (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0); - u8 tmp0xc58 =3D (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0); + u8 tmp0xc50 =3D (u8)PHY_QueryBBReg(dm_odm->Adapter, 0xC50, bMaskByte0); + u8 tmp0xc58 =3D (u8)PHY_QueryBBReg(dm_odm->Adapter, 0xC58, bMaskByte0); u32 ADDA_REG[IQK_ADDA_REG_NUM] =3D { rFPGA0_XCD_SwitchControl, rBlue_Tooth, @@ -1372,69 +1372,69 @@ static void phy_IQCalibrate_8723B( if (t =3D=3D 0) { =20 /* Save ADDA parameters, turn Path A ADDA on */ - _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo= .ADDA_backup, IQK_ADDA_REG_NUM); - _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateIn= fo.IQK_MAC_backup); - _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibra= teInfo.IQK_BB_backup, IQK_BB_REG_NUM); + _PHY_SaveADDARegisters8723B(adapter, ADDA_REG, dm_odm->RFCalibrateInfo.A= DDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8723B(adapter, IQK_MAC_REG, dm_odm->RFCalibrateInfo= .IQK_MAC_backup); + _PHY_SaveADDARegisters8723B(adapter, IQK_BB_REG_92C, dm_odm->RFCalibrate= Info.IQK_BB_backup, IQK_BB_REG_NUM); } =20 - _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T); + _PHY_PathADDAOn8723B(adapter, ADDA_REG, is2T); =20 /* no serial mode */ =20 /* save RF path for 8723B */ -/* Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ -/* Path_SEL_RF =3D PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xff= fff); */ +/* Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); */ +/* Path_SEL_RF =3D PHY_QueryRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, 0xfff= ff); */ =20 /* MAC settings */ - _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibra= teInfo.IQK_MAC_backup); + _PHY_MACSettingCalibration8723B(adapter, IQK_MAC_REG, dm_odm->RFCalibrate= Info.IQK_MAC_backup); =20 /* BB setting */ - /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */ - PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a056= 00); - PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22= 204000); + /* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */ + PHY_SetBBReg(dm_odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a0560= 0); + PHY_SetBBReg(dm_odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x222= 04000); =20 =20 -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);= */ -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);= */ -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); = */ -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); = */ +/* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); = */ +/* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); = */ +/* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */ +/* PHY_SetBBReg(dm_odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */ =20 =20 /* RX IQ calibration setting for 8723B D cut large current issue when leav= ing IPS */ =20 - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 30000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xf7fb7); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd= ); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x3= 0000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= f7fb7); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); =20 /* path A TX IQK */ for (i =3D 0 ; i < retryCount ; i++) { - PathAOK =3D phy_PathA_IQK_8723B(padapter, is2T, RF_Path); + PathAOK =3D phy_PathA_IQK_8723B(adapter, is2T, RF_Path); /* if (PathAOK =3D=3D 0x03) { */ if (PathAOK =3D=3D 0x01) { /* Path A Tx IQK Success */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] =3D PHY_QueryRFReg(pDM_Odm->A= dapter, RF_PATH_A, 0x8, bRFRegOffsetMask); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + dm_odm->RFCalibrateInfo.TxLOK[RF_PATH_A] =3D PHY_QueryRFReg(dm_odm->Ada= pter, RF_PATH_A, 0x8, bRFRegOffsetMask); =20 - result[t][0] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQ= K_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK= _A, bMaskDWord)&0x3FF0000)>>16; + result[t][0] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK= _A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_= A, bMaskDWord)&0x3FF0000)>>16; break; } } =20 /* path A RXIQK */ for (i =3D 0 ; i < retryCount ; i++) { - PathAOK =3D phy_PathA_RxIQK8723B(padapter, is2T, RF_Path); + PathAOK =3D phy_PathA_RxIQK8723B(adapter, is2T, RF_Path); if (PathAOK =3D=3D 0x03) { -/* result[t][0] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before= _IQK_A, bMaskDWord)&0x3FF0000)>>16; */ -/* result[t][1] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_= IQK_A, bMaskDWord)&0x3FF0000)>>16; */ - result[t][2] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQ= K_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK= _A_2, bMaskDWord)&0x3FF0000)>>16; +/* result[t][0] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_= IQK_A, bMaskDWord)&0x3FF0000)>>16; */ +/* result[t][1] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_I= QK_A, bMaskDWord)&0x3FF0000)>>16; */ + result[t][2] =3D (PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_Before_IQK= _A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] =3D (PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_= A_2, bMaskDWord)&0x3FF0000)>>16; break; } } @@ -1447,26 +1447,26 @@ static void phy_IQCalibrate_8723B( =20 /* path B TX IQK */ for (i =3D 0 ; i < retryCount ; i++) { - PathBOK =3D phy_PathB_IQK_8723B(padapter); + PathBOK =3D phy_PathB_IQK_8723B(adapter); if (PathBOK =3D=3D 0x01) { /* Path B Tx IQK Success */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); - pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] =3D PHY_QueryRFReg(pDM_Odm->= Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + dm_odm->RFCalibrateInfo.TxLOK[RF_PATH_B] =3D PHY_QueryRFReg(dm_odm->Ad= apter, RF_PATH_B, 0x8, bRFRegOffsetMask); =20 - result[t][4] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQ= K_A, bMaskDWord)&0x3FF0000)>>16; - result[t][5] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK= _A, bMaskDWord)&0x3FF0000)>>16; + result[t][4] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_IQK= _A, bMaskDWord)&0x3FF0000)>>16; + result[t][5] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_IQK_= A, bMaskDWord)&0x3FF0000)>>16; break; } } =20 /* path B RX IQK */ for (i =3D 0 ; i < retryCount ; i++) { - PathBOK =3D phy_PathB_RxIQK8723B(padapter, is2T); + PathBOK =3D phy_PathB_RxIQK8723B(adapter, is2T); if (PathBOK =3D=3D 0x03) { -/* result[t][0] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before= _IQK_A, bMaskDWord)&0x3FF0000)>>16; */ -/* result[t][1] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_= IQK_A, bMaskDWord)&0x3FF0000)>>16; */ - result[t][6] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQ= K_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK= _A_2, bMaskDWord)&0x3FF0000)>>16; +/* result[t][0] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_Before_= IQK_A, bMaskDWord)&0x3FF0000)>>16; */ +/* result[t][1] =3D (PHY_QueryBBReg(dm_odm->Adapter, rTx_Power_After_I= QK_A, bMaskDWord)&0x3FF0000)>>16; */ + result[t][6] =3D (PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_Before_IQK= _A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] =3D (PHY_QueryBBReg(dm_odm->Adapter, rRx_Power_After_IQK_= A_2, bMaskDWord)&0x3FF0000)>>16; break; } } @@ -1475,120 +1475,120 @@ static void phy_IQCalibrate_8723B( } =20 /* Back to BB mode, load original value */ - PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0); + PHY_SetBBReg(dm_odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0); =20 if (t !=3D 0) { /* Reload ADDA power saving parameters */ - _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateIn= fo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_ReloadADDARegisters8723B(adapter, ADDA_REG, dm_odm->RFCalibrateInfo= .ADDA_backup, IQK_ADDA_REG_NUM); =20 /* Reload MAC parameters */ - _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrate= Info.IQK_MAC_backup); + _PHY_ReloadMACRegisters8723B(adapter, IQK_MAC_REG, dm_odm->RFCalibrateIn= fo.IQK_MAC_backup); =20 - _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalib= rateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + _PHY_ReloadADDARegisters8723B(adapter, IQK_BB_REG_92C, dm_odm->RFCalibra= teInfo.IQK_BB_backup, IQK_BB_REG_NUM); =20 /* Reload RF path */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF)= ; */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);= */ =20 /* Allen initial gain 0xc50 */ /* Restore RX initial gain */ - PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50); - PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50); + PHY_SetBBReg(dm_odm->Adapter, 0xc50, bMaskByte0, 0x50); + PHY_SetBBReg(dm_odm->Adapter, 0xc50, bMaskByte0, tmp0xc50); if (is2T) { - PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50); - PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58); + PHY_SetBBReg(dm_odm->Adapter, 0xc58, bMaskByte0, 0x50); + PHY_SetBBReg(dm_odm->Adapter, 0xc58, bMaskByte0, tmp0xc58); } =20 /* load 0xe30 IQC default value */ - PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(dm_odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(dm_odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); =20 } =20 } =20 =20 -static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T) +static void phy_LCCalibrate_8723B(struct dm_odm_t *dm_odm, bool is2T) { u8 tmpReg; u32 RF_Amode =3D 0, RF_Bmode =3D 0, LC_Cal; - struct adapter *padapter =3D pDM_Odm->Adapter; + struct adapter *adapter =3D dm_odm->Adapter; =20 /* Check continuous TX and Packet TX */ - tmpReg =3D rtw_read8(pDM_Odm->Adapter, 0xd03); + tmpReg =3D rtw_read8(dm_odm->Adapter, 0xd03); =20 if ((tmpReg&0x70) !=3D 0) /* Deal with contisuous TX case */ - rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continu= ous TX */ + rtw_write8(dm_odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuo= us TX */ else /* Deal with Packet TX case */ - rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */ + rtw_write8(dm_odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */ =20 if ((tmpReg&0x70) !=3D 0) { /* 1. Read original RF mode */ /* Path-A */ - RF_Amode =3D PHY_QueryRFReg(padapter, RF_PATH_A, RF_AC, bMask12Bits); + RF_Amode =3D PHY_QueryRFReg(adapter, RF_PATH_A, RF_AC, bMask12Bits); =20 /* Path-B */ if (is2T) - RF_Bmode =3D PHY_QueryRFReg(padapter, RF_PATH_B, RF_AC, bMask12Bits); + RF_Bmode =3D PHY_QueryRFReg(adapter, RF_PATH_B, RF_AC, bMask12Bits); =20 /* 2. Set RF mode =3D standby mode */ /* Path-A */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&= 0x8FFFF)|0x10000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0= x8FFFF)|0x10000); =20 /* Path-B */ if (is2T) - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode= &0x8FFFF)|0x10000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&= 0x8FFFF)|0x10000); } =20 /* 3. Read RF reg18 */ - LC_Cal =3D PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); + LC_Cal =3D PHY_QueryRFReg(adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); =20 /* 4. Set LC calibration begin bit15 */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0= ); /* LDO ON */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|= 0x08000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0)= ; /* LDO ON */ + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0= x08000); =20 mdelay(100); =20 - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0= ); /* LDO OFF */ + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0)= ; /* LDO OFF */ =20 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ - if (pDM_Odm->SupportInterface =3D=3D ODM_ITRF_SDIO && pDM_Odm->PackageTyp= e >=3D 0x2) { - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal= ); + if (dm_odm->SupportInterface =3D=3D ODM_ITRF_SDIO && dm_odm->PackageType = >=3D 0x2) { + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); } =20 /* Restore original situation */ if ((tmpReg&0x70) !=3D 0) { /* Deal with contisuous TX case */ /* Path-A */ - rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + rtw_write8(dm_odm->Adapter, 0xd03, tmpReg); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); =20 /* Path-B */ if (is2T) - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); } else /* Deal with Packet TX case */ - rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00); + rtw_write8(dm_odm->Adapter, REG_TXPAUSE, 0x00); } =20 /* IQK version:V2.5 20140123 */ /* IQK is controlled by Is2ant, RF path */ void PHY_IQCalibrate_8723B( - struct adapter *padapter, - bool bReCovery, - bool bRestore, + struct adapter *adapter, + bool recovery, + bool restore, bool Is2ant, /* false:1ant, true:2-ant */ u8 RF_Path /* 0:S1, 1:S0 */ ) { - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); + struct hal_com_data *hal_data =3D GET_HAL_DATA(adapter); =20 - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 s32 result[4][8]; /* last is final result */ u8 i, final_candidate; - bool bPathAOK, bPathBOK; + bool path_a_ok, path_b_ok; s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC, RegEC4, RegTmp =3D 0; bool is12simular, is13simular, is23simular; - bool bSingleTone =3D false, bCarrierSuppression =3D false; + bool single_tone =3D false, carrier_suppression =3D false; u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] =3D { rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, @@ -1603,76 +1603,76 @@ void PHY_IQCalibrate_8723B( /* u32 Path_SEL_BB =3D 0; */ u32 GNT_BT_default; =20 - if (!ODM_CheckPowerStatus(padapter)) + if (!ODM_CheckPowerStatus(adapter)) return; =20 - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) return; =20 /* 20120213 Turn on when continuous Tx to pass lab testing. (req= uired by Edlu) */ - if (bSingleTone || bCarrierSuppression) + if (single_tone || carrier_suppression) return; =20 - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) + if (dm_odm->RFCalibrateInfo.bIQKInProgress) return; =20 =20 - pDM_Odm->RFCalibrateInfo.bIQKInProgress =3D true; + dm_odm->RFCalibrateInfo.bIQKInProgress =3D true; =20 - if (bRestore) { + if (restore) { u32 offset, data; u8 path, bResult =3D SUCCESS; - struct odm_rf_cal_t *pRFCalibrateInfo =3D &pDM_Odm->RFCalibrateInfo; + struct odm_rf_cal_t *rf_calibrate_info =3D &dm_odm->RFCalibrateInfo; =20 - path =3D (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0)= =3D=3D 0x00) ? RF_PATH_A : RF_PATH_B; + path =3D (PHY_QueryBBReg(dm_odm->Adapter, rS0S1_PathSwitch, bMaskByte0) = =3D=3D 0x00) ? RF_PATH_A : RF_PATH_B; =20 /* Restore TX IQK */ for (i =3D 0; i < 3; ++i) { - offset =3D pRFCalibrateInfo->TxIQC_8723B[path][i][0]; - data =3D pRFCalibrateInfo->TxIQC_8723B[path][i][1]; + offset =3D rf_calibrate_info->TxIQC_8723B[path][i][0]; + data =3D rf_calibrate_info->TxIQC_8723B[path][i][1]; if ((offset =3D=3D 0) || (data =3D=3D 0)) { bResult =3D FAIL; break; } - PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); + PHY_SetBBReg(dm_odm->Adapter, offset, bMaskDWord, data); } =20 /* Restore RX IQK */ for (i =3D 0; i < 2; ++i) { - offset =3D pRFCalibrateInfo->RxIQC_8723B[path][i][0]; - data =3D pRFCalibrateInfo->RxIQC_8723B[path][i][1]; + offset =3D rf_calibrate_info->RxIQC_8723B[path][i][0]; + data =3D rf_calibrate_info->RxIQC_8723B[path][i][1]; if ((offset =3D=3D 0) || (data =3D=3D 0)) { bResult =3D FAIL; break; } - PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); + PHY_SetBBReg(dm_odm->Adapter, offset, bMaskDWord, data); } =20 - if (pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] =3D=3D 0) { + if (dm_odm->RFCalibrateInfo.TxLOK[RF_PATH_A] =3D=3D 0) { bResult =3D FAIL; } else { - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask= , pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A]); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask= , pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B]); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask,= dm_odm->RFCalibrateInfo.TxLOK[RF_PATH_A]); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask,= dm_odm->RFCalibrateInfo.TxLOK[RF_PATH_B]); } =20 if (bResult =3D=3D SUCCESS) return; } =20 - if (bReCovery) { - _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalib= rateInfo.IQK_BB_backup_recover, 9); + if (recovery) { + _PHY_ReloadADDARegisters8723B(adapter, IQK_BB_REG_92C, dm_odm->RFCalibra= teInfo.IQK_BB_backup_recover, 9); return; } =20 /* save default GNT_BT */ - GNT_BT_default =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord); + GNT_BT_default =3D PHY_QueryBBReg(dm_odm->Adapter, 0x764, bMaskDWord); /* Save RF Path */ -/* Path_SEL_BB =3D PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ -/* Path_SEL_RF =3D PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xff= fff); */ +/* Path_SEL_BB =3D PHY_QueryBBReg(dm_odm->Adapter, 0x948, bMaskDWord); */ +/* Path_SEL_RF =3D PHY_QueryRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, 0xfff= ff); */ =20 /* set GNT_BT =3D 0, pause BT traffic */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x764, BIT12, 0x0); */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x764, BIT11, 0x1); */ =20 =20 for (i =3D 0; i < 8; i++) { @@ -1683,18 +1683,18 @@ void PHY_IQCalibrate_8723B( } =20 final_candidate =3D 0xff; - bPathAOK =3D false; - bPathBOK =3D false; + path_a_ok =3D false; + path_b_ok =3D false; is12simular =3D false; is23simular =3D false; is13simular =3D false; =20 =20 for (i =3D 0; i < 3; i++) { - phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path); + phy_IQCalibrate_8723B(adapter, result, i, Is2ant, RF_Path); =20 if (i =3D=3D 1) { - is12simular =3D phy_SimularityCompare_8723B(padapter, result, 0, 1); + is12simular =3D phy_SimularityCompare_8723B(adapter, result, 0, 1); if (is12simular) { final_candidate =3D 0; break; @@ -1702,14 +1702,14 @@ void PHY_IQCalibrate_8723B( } =20 if (i =3D=3D 2) { - is13simular =3D phy_SimularityCompare_8723B(padapter, result, 0, 2); + is13simular =3D phy_SimularityCompare_8723B(adapter, result, 0, 2); if (is13simular) { final_candidate =3D 0; =20 break; } =20 - is23simular =3D phy_SimularityCompare_8723B(padapter, result, 1, 2); + is23simular =3D phy_SimularityCompare_8723B(adapter, result, 1, 2); if (is23simular) { final_candidate =3D 1; } else { @@ -1734,87 +1734,87 @@ void PHY_IQCalibrate_8723B( } =20 if (final_candidate !=3D 0xff) { - pDM_Odm->RFCalibrateInfo.RegE94 =3D RegE94 =3D result[final_candidate][0= ]; - pDM_Odm->RFCalibrateInfo.RegE9C =3D RegE9C =3D result[final_candidate][1= ]; + dm_odm->RFCalibrateInfo.RegE94 =3D RegE94 =3D result[final_candidate][0]; + dm_odm->RFCalibrateInfo.RegE9C =3D RegE9C =3D result[final_candidate][1]; RegEA4 =3D result[final_candidate][2]; - pDM_Odm->RFCalibrateInfo.RegEB4 =3D RegEB4 =3D result[final_candidate][4= ]; - pDM_Odm->RFCalibrateInfo.RegEBC =3D RegEBC =3D result[final_candidate][5= ]; + dm_odm->RFCalibrateInfo.RegEB4 =3D RegEB4 =3D result[final_candidate][4]; + dm_odm->RFCalibrateInfo.RegEBC =3D RegEBC =3D result[final_candidate][5]; RegEC4 =3D result[final_candidate][6]; - bPathAOK =3D bPathBOK =3D true; + path_a_ok =3D path_b_ok =3D true; } else { - pDM_Odm->RFCalibrateInfo.RegE94 =3D pDM_Odm->RFCalibrateInfo.RegEB4 =3D = 0x100; /* X default value */ - pDM_Odm->RFCalibrateInfo.RegE9C =3D pDM_Odm->RFCalibrateInfo.RegEBC =3D = 0x0; /* Y default value */ + dm_odm->RFCalibrateInfo.RegE94 =3D dm_odm->RFCalibrateInfo.RegEB4 =3D 0x= 100; /* X default value */ + dm_odm->RFCalibrateInfo.RegE9C =3D dm_odm->RFCalibrateInfo.RegEBC =3D 0x= 0; /* Y default value */ } =20 { if (RegE94 !=3D 0) - _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidat= e, (RegEA4 =3D=3D 0)); + _PHY_PathAFillIQKMatrix8723B(adapter, path_a_ok, result, final_candidat= e, (RegEA4 =3D=3D 0)); } { if (RegEB4 !=3D 0) - _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidat= e, (RegEC4 =3D=3D 0)); + _PHY_PathBFillIQKMatrix8723B(adapter, path_b_ok, result, final_candidat= e, (RegEC4 =3D=3D 0)); } =20 /* To Fix BSOD when final_candidate is 0xff */ /* by sherry 20120321 */ if (final_candidate < 4) { for (i =3D 0; i < IQK_MATRIX_REG_NUM; i++) - pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] =3D result= [final_candidate][i]; + dm_odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] =3D result[= final_candidate][i]; } =20 - _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrat= eInfo.IQK_BB_backup_recover, 9); + _PHY_SaveADDARegisters8723B(adapter, IQK_BB_REG_92C, dm_odm->RFCalibrateI= nfo.IQK_BB_backup_recover, 9); =20 /* restore GNT_BT */ - PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default); + PHY_SetBBReg(dm_odm->Adapter, 0x764, bMaskDWord, GNT_BT_default); /* Restore RF Path */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);= */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ +/* PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); = */ =20 /* Resotr RX mode table parameter */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x= 18000); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0= x0001f); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0= xe6177); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd= ); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x1= 8000); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x= 0001f); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x= e6177); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1); + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); =20 /* set GNT_BT =3D HW control */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x764, BIT12, 0x0); */ +/* PHY_SetBBReg(dm_odm->Adapter, 0x764, BIT11, 0x0); */ =20 if (Is2ant) { if (RF_Path =3D=3D 0x0) /* S1 */ - ODM_SetIQCbyRFpath(pDM_Odm, 0); + ODM_SetIQCbyRFpath(dm_odm, 0); else /* S0 */ - ODM_SetIQCbyRFpath(pDM_Odm, 1); + ODM_SetIQCbyRFpath(dm_odm, 1); } =20 - pDM_Odm->RFCalibrateInfo.bIQKInProgress =3D false; + dm_odm->RFCalibrateInfo.bIQKInProgress =3D false; } =20 =20 -void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm) +void PHY_LCCalibrate_8723B(struct dm_odm_t *dm_odm) { - bool bSingleTone =3D false, bCarrierSuppression =3D false; + bool single_tone =3D false, carrier_suppression =3D false; u32 timeout =3D 2000, timecount =3D 0; =20 - if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION)) return; =20 /* 20120213 Turn on when continuous Tx to pass lab testing. (req= uired by Edlu) */ - if (bSingleTone || bCarrierSuppression) + if (single_tone || carrier_suppression) return; =20 - while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + while (*(dm_odm->pbScanInProcess) && timecount < timeout) { mdelay(50); timecount +=3D 50; } =20 - pDM_Odm->RFCalibrateInfo.bLCKInProgress =3D true; + dm_odm->RFCalibrateInfo.bLCKInProgress =3D true; =20 =20 - phy_LCCalibrate_8723B(pDM_Odm, false); + phy_LCCalibrate_8723B(dm_odm, false); =20 =20 - pDM_Odm->RFCalibrateInfo.bLCKInProgress =3D false; + dm_odm->RFCalibrateInfo.bLCKInProgress =3D false; } diff --git a/drivers/staging/rtl8723bs/hal/odm.c b/drivers/staging/rtl8723b= s/hal/odm.c index 8d6131f0ad47..91fed68bbb3c 100644 --- a/drivers/staging/rtl8723bs/hal/odm.c +++ b/drivers/staging/rtl8723bs/hal/odm.c @@ -281,45 +281,45 @@ u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =3D { =20 /* Remove Edca by Yu Chen */ =20 -static void odm_CommonInfoSelfInit(struct dm_odm_t *pDM_Odm) +static void odm_CommonInfoSelfInit(struct dm_odm_t *dm_odm) { - pDM_Odm->bCckHighPower =3D (bool) PHY_QueryBBReg(pDM_Odm->Adapter, ODM_RE= G(CCK_RPT_FORMAT, pDM_Odm), ODM_BIT(CCK_RPT_FORMAT, pDM_Odm)); - pDM_Odm->RFPathRxEnable =3D (u8) PHY_QueryBBReg(pDM_Odm->Adapter, ODM_REG= (BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm)); + dm_odm->bCckHighPower =3D (bool) PHY_QueryBBReg(dm_odm->Adapter, ODM_REG(= CCK_RPT_FORMAT, dm_odm), ODM_BIT(CCK_RPT_FORMAT, dm_odm)); + dm_odm->RFPathRxEnable =3D (u8) PHY_QueryBBReg(dm_odm->Adapter, ODM_REG(B= B_RX_PATH, dm_odm), ODM_BIT(BB_RX_PATH, dm_odm)); =20 - pDM_Odm->TxRate =3D 0xFF; + dm_odm->TxRate =3D 0xFF; } =20 -static void odm_CommonInfoSelfUpdate(struct dm_odm_t *pDM_Odm) +static void odm_CommonInfoSelfUpdate(struct dm_odm_t *dm_odm) { u8 EntryCnt =3D 0; u8 i; - PSTA_INFO_T pEntry; + PSTA_INFO_T entry; =20 - if (*(pDM_Odm->pBandWidth) =3D=3D ODM_BW40M) { - if (*(pDM_Odm->pSecChOffset) =3D=3D 1) - pDM_Odm->ControlChannel =3D *(pDM_Odm->pChannel)-2; - else if (*(pDM_Odm->pSecChOffset) =3D=3D 2) - pDM_Odm->ControlChannel =3D *(pDM_Odm->pChannel)+2; + if (*(dm_odm->pBandWidth) =3D=3D ODM_BW40M) { + if (*(dm_odm->pSecChOffset) =3D=3D 1) + dm_odm->ControlChannel =3D *(dm_odm->pChannel)-2; + else if (*(dm_odm->pSecChOffset) =3D=3D 2) + dm_odm->ControlChannel =3D *(dm_odm->pChannel)+2; } else - pDM_Odm->ControlChannel =3D *(pDM_Odm->pChannel); + dm_odm->ControlChannel =3D *(dm_odm->pChannel); =20 for (i =3D 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry =3D pDM_Odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) + entry =3D dm_odm->pODM_StaInfo[i]; + if (IS_STA_VALID(entry)) EntryCnt++; } =20 if (EntryCnt =3D=3D 1) - pDM_Odm->bOneEntryOnly =3D true; + dm_odm->bOneEntryOnly =3D true; else - pDM_Odm->bOneEntryOnly =3D false; + dm_odm->bOneEntryOnly =3D false; } =20 -static void odm_CmnInfoInit_Debug(struct dm_odm_t *pDM_Odm) +static void odm_CmnInfoInit_Debug(struct dm_odm_t *dm_odm) { } =20 -static void odm_BasicDbgMessage(struct dm_odm_t *pDM_Odm) +static void odm_BasicDbgMessage(struct dm_odm_t *dm_odm) { } =20 @@ -330,39 +330,39 @@ static void odm_BasicDbgMessage(struct dm_odm_t *pDM_= Odm) /* 3 Rate Adaptive */ /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -static void odm_RateAdaptiveMaskInit(struct dm_odm_t *pDM_Odm) +static void odm_RateAdaptiveMaskInit(struct dm_odm_t *dm_odm) { - struct odm_rate_adaptive *pOdmRA =3D &pDM_Odm->RateAdaptive; + struct odm_rate_adaptive *odm_ra =3D &dm_odm->RateAdaptive; =20 - pOdmRA->Type =3D DM_Type_ByDriver; - if (pOdmRA->Type =3D=3D DM_Type_ByDriver) - pDM_Odm->bUseRAMask =3D true; + odm_ra->Type =3D DM_Type_ByDriver; + if (odm_ra->Type =3D=3D DM_Type_ByDriver) + dm_odm->bUseRAMask =3D true; else - pDM_Odm->bUseRAMask =3D false; + dm_odm->bUseRAMask =3D false; =20 - pOdmRA->RATRState =3D DM_RATR_STA_INIT; - pOdmRA->LdpcThres =3D 35; - pOdmRA->bUseLdpc =3D false; - pOdmRA->HighRSSIThresh =3D 50; - pOdmRA->LowRSSIThresh =3D 20; + odm_ra->RATRState =3D DM_RATR_STA_INIT; + odm_ra->LdpcThres =3D 35; + odm_ra->bUseLdpc =3D false; + odm_ra->HighRSSIThresh =3D 50; + odm_ra->LowRSSIThresh =3D 20; } =20 u32 ODM_Get_Rate_Bitmap( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, u32 macid, u32 ra_mask, u8 rssi_level ) { - PSTA_INFO_T pEntry; + PSTA_INFO_T entry; u32 rate_bitmap =3D 0; u8 WirelessMode; =20 - pEntry =3D pDM_Odm->pODM_StaInfo[macid]; - if (!IS_STA_VALID(pEntry)) + entry =3D dm_odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(entry)) return ra_mask; =20 - WirelessMode =3D pEntry->wireless_mode; + WirelessMode =3D entry->wireless_mode; =20 switch (WirelessMode) { case ODM_WM_B: @@ -396,7 +396,7 @@ u32 ODM_Get_Rate_Bitmap( else if (rssi_level =3D=3D DM_RATR_STA_MIDDLE) rate_bitmap =3D 0x000ff000; else { - if (*(pDM_Odm->pBandWidth) =3D=3D ODM_BW40M) + if (*(dm_odm->pBandWidth) =3D=3D ODM_BW40M) rate_bitmap =3D 0x000ff015; else rate_bitmap =3D 0x000ff005; @@ -412,25 +412,25 @@ u32 ODM_Get_Rate_Bitmap( =20 } =20 -static void odm_RefreshRateAdaptiveMaskCE(struct dm_odm_t *pDM_Odm) +static void odm_RefreshRateAdaptiveMaskCE(struct dm_odm_t *dm_odm) { u8 i; - struct adapter *padapter =3D pDM_Odm->Adapter; + struct adapter *padapter =3D dm_odm->Adapter; =20 if (padapter->bDriverStopped) return; =20 - if (!pDM_Odm->bUseRAMask) + if (!dm_odm->bUseRAMask) return; =20 for (i =3D 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - PSTA_INFO_T pstat =3D pDM_Odm->pODM_StaInfo[i]; + PSTA_INFO_T pstat =3D dm_odm->pODM_StaInfo[i]; =20 if (IS_STA_VALID(pstat)) { if (is_multicast_ether_addr(pstat->hwaddr)) /* if (psta->mac_id =3D=3D= 1) */ continue; =20 - if (true =3D=3D ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedS= moothedPWDB, false, &pstat->rssi_level)) { + if (true =3D=3D ODM_RAStateCheck(dm_odm, pstat->rssi_stat.UndecoratedSm= oothedPWDB, false, &pstat->rssi_level)) { rtw_hal_update_ra_mask(pstat, pstat->rssi_level); } =20 @@ -455,34 +455,34 @@ static void odm_RefreshRateAdaptiveMaskCE(struct dm_o= dm_t *pDM_Odm) * * ------------------------------------------------------------------------= -- */ -static void odm_RefreshRateAdaptiveMask(struct dm_odm_t *pDM_Odm) +static void odm_RefreshRateAdaptiveMask(struct dm_odm_t *dm_odm) { =20 - if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) + if (!(dm_odm->SupportAbility & ODM_BB_RA_MASK)) return; =20 - odm_RefreshRateAdaptiveMaskCE(pDM_Odm); + odm_RefreshRateAdaptiveMaskCE(dm_odm); } =20 /* Return Value: bool */ /* - true: RATRState is changed. */ bool ODM_RAStateCheck( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, s32 RSSI, - bool bForceUpdate, - u8 *pRATRState + bool force_update, + u8 *ratrstate ) { - struct odm_rate_adaptive *pRA =3D &pDM_Odm->RateAdaptive; + struct odm_rate_adaptive *ra =3D &dm_odm->RateAdaptive; const u8 GoUpGap =3D 5; - u8 HighRSSIThreshForRA =3D pRA->HighRSSIThresh; - u8 LowRSSIThreshForRA =3D pRA->LowRSSIThresh; + u8 HighRSSIThreshForRA =3D ra->HighRSSIThresh; + u8 LowRSSIThreshForRA =3D ra->LowRSSIThresh; u8 RATRState; =20 /* Threshold Adjustment: */ /* when RSSI state trends to go up one or two levels, make sure RSSI is = high enough. */ /* Here GoUpGap is added to solve the boundary's level alternation issue= . */ - switch (*pRATRState) { + switch (*ratrstate) { case DM_RATR_STA_INIT: case DM_RATR_STA_HIGH: break; @@ -497,8 +497,8 @@ bool ODM_RAStateCheck( break; =20 default: - netdev_dbg(pDM_Odm->Adapter->pnetdev, - "wrong rssi level setting %d !", *pRATRState); + netdev_dbg(dm_odm->Adapter->pnetdev, + "wrong rssi level setting %d !", *ratrstate); break; } =20 @@ -510,8 +510,8 @@ bool ODM_RAStateCheck( else RATRState =3D DM_RATR_STA_LOW; =20 - if (*pRATRState !=3D RATRState || bForceUpdate) { - *pRATRState =3D RATRState; + if (*ratrstate !=3D RATRState || force_update) { + *ratrstate =3D RATRState; return true; } =20 @@ -524,24 +524,24 @@ bool ODM_RAStateCheck( /* 3 RSSI Monitor */ /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -static void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm) +static void odm_RSSIMonitorInit(struct dm_odm_t *dm_odm) { - struct ra_t *pRA_Table =3D &pDM_Odm->DM_RA_Table; + struct ra_t *ra_Table =3D &dm_odm->DM_RA_Table; =20 - pRA_Table->firstconnect =3D false; + ra_Table->firstconnect =3D false; =20 } =20 static void FindMinimumRSSI(struct adapter *padapter) { - struct hal_com_data *pHalData =3D GET_HAL_DATA(padapter); - struct dm_priv *pdmpriv =3D &pHalData->dmpriv; - struct dm_odm_t *pDM_Odm =3D &pHalData->odmpriv; + struct hal_com_data *hal_data =3D GET_HAL_DATA(padapter); + struct dm_priv *pdmpriv =3D &hal_data->dmpriv; + struct dm_odm_t *dm_odm =3D &hal_data->odmpriv; =20 /* 1 1.Determine the minimum RSSI */ =20 if ( - (pDM_Odm->bLinked !=3D true) && + (dm_odm->bLinked !=3D true) && (pdmpriv->EntryMinUndecoratedSmoothedPWDB =3D=3D 0) ) { pdmpriv->MinUndecoratedPWDBForDM =3D 0; @@ -549,28 +549,28 @@ static void FindMinimumRSSI(struct adapter *padapter) pdmpriv->MinUndecoratedPWDBForDM =3D pdmpriv->EntryMinUndecoratedSmoothe= dPWDB; } =20 -static void odm_RSSIMonitorCheckCE(struct dm_odm_t *pDM_Odm) +static void odm_RSSIMonitorCheckCE(struct dm_odm_t *dm_odm) { - struct adapter *Adapter =3D pDM_Odm->Adapter; - struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv =3D &pHalData->dmpriv; + struct adapter *Adapter =3D dm_odm->Adapter; + struct hal_com_data *hal_data =3D GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv =3D &hal_data->dmpriv; int i; - int tmpEntryMaxPWDB =3D 0, tmpEntryMinPWDB =3D 0xff; + int tmentryMaxPWDB =3D 0, tmentryMinPWDB =3D 0xff; u8 sta_cnt =3D 0; u32 PWDB_rssi[NUM_STA] =3D {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ - struct ra_t *pRA_Table =3D &pDM_Odm->DM_RA_Table; + struct ra_t *ra_Table =3D &dm_odm->DM_RA_Table; =20 - if (pDM_Odm->bLinked !=3D true) + if (dm_odm->bLinked !=3D true) return; =20 - pRA_Table->firstconnect =3D pDM_Odm->bLinked; + ra_Table->firstconnect =3D dm_odm->bLinked; =20 /* if (check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|W= IFI_ADHOC_MASTER_STATE) =3D=3D true) */ { struct sta_info *psta; =20 for (i =3D 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - psta =3D pDM_Odm->pODM_StaInfo[i]; + psta =3D dm_odm->pODM_StaInfo[i]; if (IS_STA_VALID(psta)) { if (is_multicast_ether_addr(psta->hwaddr)) /* if (psta->mac_id =3D=3D= 1) */ continue; @@ -578,11 +578,11 @@ static void odm_RSSIMonitorCheckCE(struct dm_odm_t *p= DM_Odm) if (psta->rssi_stat.UndecoratedSmoothedPWDB =3D=3D (-1)) continue; =20 - if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) - tmpEntryMinPWDB =3D psta->rssi_stat.UndecoratedSmoothedPWDB; + if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmentryMinPWDB) + tmentryMinPWDB =3D psta->rssi_stat.UndecoratedSmoothedPWDB; =20 - if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) - tmpEntryMaxPWDB =3D psta->rssi_stat.UndecoratedSmoothedPWDB; + if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmentryMaxPWDB) + tmentryMaxPWDB =3D psta->rssi_stat.UndecoratedSmoothedPWDB; =20 if (psta->rssi_stat.UndecoratedSmoothedPWDB !=3D (-1)) PWDB_rssi[sta_cnt++] =3D (psta->mac_id | (psta->rssi_stat.Undecorated= SmoothedPWDB<<16)); @@ -591,7 +591,7 @@ static void odm_RSSIMonitorCheckCE(struct dm_odm_t *pDM= _Odm) =20 for (i =3D 0; i < sta_cnt; i++) { if (PWDB_rssi[i] !=3D (0)) { - if (pHalData->fw_ractrl =3D=3D true)/* Report every sta's RSSI to FW = */ + if (hal_data->fw_ractrl =3D=3D true)/* Report every sta's RSSI to FW = */ rtl8723b_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i])); } } @@ -599,63 +599,63 @@ static void odm_RSSIMonitorCheckCE(struct dm_odm_t *p= DM_Odm) =20 =20 =20 - if (tmpEntryMaxPWDB !=3D 0) /* If associated entry is found */ - pdmpriv->EntryMaxUndecoratedSmoothedPWDB =3D tmpEntryMaxPWDB; + if (tmentryMaxPWDB !=3D 0) /* If associated entry is found */ + pdmpriv->EntryMaxUndecoratedSmoothedPWDB =3D tmentryMaxPWDB; else pdmpriv->EntryMaxUndecoratedSmoothedPWDB =3D 0; =20 - if (tmpEntryMinPWDB !=3D 0xff) /* If associated entry is found */ - pdmpriv->EntryMinUndecoratedSmoothedPWDB =3D tmpEntryMinPWDB; + if (tmentryMinPWDB !=3D 0xff) /* If associated entry is found */ + pdmpriv->EntryMinUndecoratedSmoothedPWDB =3D tmentryMinPWDB; else pdmpriv->EntryMinUndecoratedSmoothedPWDB =3D 0; =20 FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */ =20 - pDM_Odm->RSSI_Min =3D pdmpriv->MinUndecoratedPWDBForDM; - /* ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->= MinUndecoratedPWDBForDM); */ + dm_odm->RSSI_Min =3D pdmpriv->MinUndecoratedPWDBForDM; + /* ODM_CmnInfoUpdate(&hal_data->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->= MinUndecoratedPWDBForDM); */ } =20 -static void odm_RSSIMonitorCheck(struct dm_odm_t *pDM_Odm) +static void odm_RSSIMonitorCheck(struct dm_odm_t *dm_odm) { - if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + if (!(dm_odm->SupportAbility & ODM_BB_RSSI_MONITOR)) return; =20 - odm_RSSIMonitorCheckCE(pDM_Odm); + odm_RSSIMonitorCheckCE(dm_odm); =20 } /* odm_RSSIMonitorCheck */ =20 /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* 3 SW Antenna Diversity */ /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ -static void odm_SwAntDetectInit(struct dm_odm_t *pDM_Odm) +static void odm_SwAntDetectInit(struct dm_odm_t *dm_odm) { - struct swat_t *pDM_SWAT_Table =3D &pDM_Odm->DM_SWAT_Table; + struct swat_t *dm_swat_table =3D &dm_odm->DM_SWAT_Table; =20 - pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c =3D rtw_read32(pDM_Odm->Adapter, rD= PDT_control); - pDM_SWAT_Table->PreAntenna =3D MAIN_ANT; - pDM_SWAT_Table->CurAntenna =3D MAIN_ANT; - pDM_SWAT_Table->SWAS_NoLink_State =3D 0; + dm_swat_table->SWAS_NoLink_BK_Reg92c =3D rtw_read32(dm_odm->Adapter, rDPD= T_control); + dm_swat_table->PreAntenna =3D MAIN_ANT; + dm_swat_table->CurAntenna =3D MAIN_ANT; + dm_swat_table->SWAS_NoLink_State =3D 0; } =20 /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* 3 Tx Power Tracking */ /* 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -static u8 getSwingIndex(struct dm_odm_t *pDM_Odm) +static u8 getSwingIndex(struct dm_odm_t *dm_odm) { - struct adapter *Adapter =3D pDM_Odm->Adapter; + struct adapter *Adapter =3D dm_odm->Adapter; u8 i =3D 0; u32 bbSwing; u32 swingTableSize; - u32 *pSwingTable; + u32 *swing_table; =20 bbSwing =3D PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); =20 - pSwingTable =3D OFDMSwingTable_New; + swing_table =3D OFDMSwingTable_New; swingTableSize =3D OFDM_TABLE_SIZE; =20 for (i =3D 0; i < swingTableSize; ++i) { - u32 tableValue =3D pSwingTable[i]; + u32 tableValue =3D swing_table[i]; =20 if (tableValue >=3D 0x100000) tableValue >>=3D 22; @@ -665,62 +665,62 @@ static u8 getSwingIndex(struct dm_odm_t *pDM_Odm) return i; } =20 -void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm) +void odm_TXPowerTrackingInit(struct dm_odm_t *dm_odm) { - u8 defaultSwingIndex =3D getSwingIndex(pDM_Odm); + u8 defaultSwingIndex =3D getSwingIndex(dm_odm); u8 p =3D 0; - struct adapter *Adapter =3D pDM_Odm->Adapter; - struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); + struct adapter *Adapter =3D dm_odm->Adapter; + struct hal_com_data *hal_data =3D GET_HAL_DATA(Adapter); =20 =20 - struct dm_priv *pdmpriv =3D &pHalData->dmpriv; + struct dm_priv *pdmpriv =3D &hal_data->dmpriv; =20 pdmpriv->bTXPowerTracking =3D true; pdmpriv->TXPowercount =3D 0; pdmpriv->bTXPowerTrackingInit =3D false; =20 - if (*(pDM_Odm->mp_mode) !=3D 1) + if (*(dm_odm->mp_mode) !=3D 1) pdmpriv->TxPowerTrackControl =3D true; else pdmpriv->TxPowerTrackControl =3D false; =20 - /* pDM_Odm->RFCalibrateInfo.TxPowerTrackControl =3D true; */ - pDM_Odm->RFCalibrateInfo.ThermalValue =3D pHalData->EEPROMThermalMeter; - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK =3D pHalData->EEPROMThermalMete= r; - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK =3D pHalData->EEPROMThermalMete= r; + /* dm_odm->RFCalibrateInfo.TxPowerTrackControl =3D true; */ + dm_odm->RFCalibrateInfo.ThermalValue =3D hal_data->EEPROMThermalMeter; + dm_odm->RFCalibrateInfo.ThermalValue_IQK =3D hal_data->EEPROMThermalMeter; + dm_odm->RFCalibrateInfo.ThermalValue_LCK =3D hal_data->EEPROMThermalMeter; =20 /* The index of "0 dB" in SwingTable. */ - pDM_Odm->DefaultOfdmIndex =3D (defaultSwingIndex >=3D OFDM_TABLE_SIZE) ? = 30 : defaultSwingIndex; - pDM_Odm->DefaultCckIndex =3D 20; + dm_odm->DefaultOfdmIndex =3D (defaultSwingIndex >=3D OFDM_TABLE_SIZE) ? 3= 0 : defaultSwingIndex; + dm_odm->DefaultCckIndex =3D 20; =20 - pDM_Odm->BbSwingIdxCckBase =3D pDM_Odm->DefaultCckIndex; - pDM_Odm->RFCalibrateInfo.CCK_index =3D pDM_Odm->DefaultCckIndex; + dm_odm->BbSwingIdxCckBase =3D dm_odm->DefaultCckIndex; + dm_odm->RFCalibrateInfo.CCK_index =3D dm_odm->DefaultCckIndex; =20 for (p =3D RF_PATH_A; p < MAX_RF_PATH; ++p) { - pDM_Odm->BbSwingIdxOfdmBase[p] =3D pDM_Odm->DefaultOfdmIndex; - pDM_Odm->RFCalibrateInfo.OFDM_index[p] =3D pDM_Odm->DefaultOfdmIndex; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] =3D 0; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] =3D 0; - pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] =3D 0; + dm_odm->BbSwingIdxOfdmBase[p] =3D dm_odm->DefaultOfdmIndex; + dm_odm->RFCalibrateInfo.OFDM_index[p] =3D dm_odm->DefaultOfdmIndex; + dm_odm->RFCalibrateInfo.DeltaPowerIndex[p] =3D 0; + dm_odm->RFCalibrateInfo.DeltaPowerIndexLast[p] =3D 0; + dm_odm->RFCalibrateInfo.PowerIndexOffset[p] =3D 0; } =20 } =20 -void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm) +void ODM_TXPowerTrackingCheck(struct dm_odm_t *dm_odm) { - struct adapter *Adapter =3D pDM_Odm->Adapter; + struct adapter *Adapter =3D dm_odm->Adapter; =20 - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + if (!(dm_odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) return; =20 - if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16= ), 0x03); + if (!dm_odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ + PHY_SetRFReg(dm_odm->Adapter, RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16)= , 0x03); =20 - pDM_Odm->RFCalibrateInfo.TM_Trigger =3D 1; + dm_odm->RFCalibrateInfo.TM_Trigger =3D 1; return; } else { ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); - pDM_Odm->RFCalibrateInfo.TM_Trigger =3D 0; + dm_odm->RFCalibrateInfo.TM_Trigger =3D 0; } } =20 @@ -731,26 +731,26 @@ void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Od= m) /* */ /* 2011/09/21 MH Add to describe different team necessary resource alloca= te?? */ /* */ -void ODM_DMInit(struct dm_odm_t *pDM_Odm) +void ODM_DMInit(struct dm_odm_t *dm_odm) { =20 - odm_CommonInfoSelfInit(pDM_Odm); - odm_CmnInfoInit_Debug(pDM_Odm); - odm_DIGInit(pDM_Odm); - odm_NHMCounterStatisticsInit(pDM_Odm); - odm_AdaptivityInit(pDM_Odm); - odm_RateAdaptiveMaskInit(pDM_Odm); - ODM_CfoTrackingInit(pDM_Odm); - ODM_EdcaTurboInit(pDM_Odm); - odm_RSSIMonitorInit(pDM_Odm); - odm_TXPowerTrackingInit(pDM_Odm); + odm_CommonInfoSelfInit(dm_odm); + odm_CmnInfoInit_Debug(dm_odm); + odm_DIGInit(dm_odm); + odm_NHMCounterStatisticsInit(dm_odm); + odm_AdaptivityInit(dm_odm); + odm_RateAdaptiveMaskInit(dm_odm); + ODM_CfoTrackingInit(dm_odm); + ODM_EdcaTurboInit(dm_odm); + odm_RSSIMonitorInit(dm_odm); + odm_TXPowerTrackingInit(dm_odm); =20 - ODM_ClearTxPowerTrackingState(pDM_Odm); + ODM_ClearTxPowerTrackingState(dm_odm); =20 - odm_DynamicBBPowerSavingInit(pDM_Odm); - odm_DynamicTxPowerInit(pDM_Odm); + odm_DynamicBBPowerSavingInit(dm_odm); + odm_DynamicTxPowerInit(dm_odm); =20 - odm_SwAntDetectInit(pDM_Odm); + odm_SwAntDetectInit(dm_odm); } =20 /* */ @@ -758,58 +758,58 @@ void ODM_DMInit(struct dm_odm_t *pDM_Odm) /* You can not add any dummy function here, be care, you can only use DM = structure */ /* to perform any new ODM_DM. */ /* */ -void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm) +void ODM_DMWatchdog(struct dm_odm_t *dm_odm) { - odm_CommonInfoSelfUpdate(pDM_Odm); - odm_BasicDbgMessage(pDM_Odm); - odm_FalseAlarmCounterStatistics(pDM_Odm); - odm_NHMCounterStatistics(pDM_Odm); + odm_CommonInfoSelfUpdate(dm_odm); + odm_BasicDbgMessage(dm_odm); + odm_FalseAlarmCounterStatistics(dm_odm); + odm_NHMCounterStatistics(dm_odm); =20 - odm_RSSIMonitorCheck(pDM_Odm); + odm_RSSIMonitorCheck(dm_odm); =20 /* For CE Platform(SPRD or Tablet) */ /* 8723A or 8189ES platform */ /* NeilChen--2012--08--24-- */ /* Fix Leave LPS issue */ - if ((adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode !=3D PS_MODE_ACTIVE) /= * in LPS mode */ + if ((adapter_to_pwrctl(dm_odm->Adapter)->pwr_mode !=3D PS_MODE_ACTIVE) /*= in LPS mode */ /* */ - /* (pDM_Odm->SupportICType & (ODM_RTL8723A))|| */ - /* (pDM_Odm->SupportICType & (ODM_RTL8188E) &&(&&(((pDM_Odm->SupportInte= rface =3D=3D ODM_ITRF_SDIO))) */ + /* (dm_odm->SupportICType & (ODM_RTL8723A))|| */ + /* (dm_odm->SupportICType & (ODM_RTL8188E) &&(&&(((dm_odm->SupportInterf= ace =3D=3D ODM_ITRF_SDIO))) */ /* */ ) { - odm_DIGbyRSSI_LPS(pDM_Odm); + odm_DIGbyRSSI_LPS(dm_odm); } else - odm_DIG(pDM_Odm); + odm_DIG(dm_odm); =20 { - struct dig_t *pDM_DigTable =3D &pDM_Odm->DM_DigTable; + struct dig_t *dm_dig_table =3D &dm_odm->DM_DigTable; =20 - odm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); + odm_Adaptivity(dm_odm, dm_dig_table->CurIGValue); } - odm_CCKPacketDetectionThresh(pDM_Odm); + odm_CCKPacketDetectionThresh(dm_odm); =20 - if (*(pDM_Odm->pbPowerSaving) =3D=3D true) + if (*(dm_odm->pbPowerSaving) =3D=3D true) return; =20 =20 - odm_RefreshRateAdaptiveMask(pDM_Odm); - odm_EdcaTurboCheck(pDM_Odm); - ODM_CfoTracking(pDM_Odm); + odm_RefreshRateAdaptiveMask(dm_odm); + odm_EdcaTurboCheck(dm_odm); + ODM_CfoTracking(dm_odm); =20 - ODM_TXPowerTrackingCheck(pDM_Odm); + ODM_TXPowerTrackingCheck(dm_odm); =20 - /* odm_EdcaTurboCheck(pDM_Odm); */ + /* odm_EdcaTurboCheck(dm_odm); */ =20 /* 2010.05.30 LukeLee: For CE platform, files in IC subfolders may not be= included to be compiled, */ /* so compile flags must be left here to prevent from compile errors */ - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt =3D 0; + dm_odm->PhyDbgInfo.NumQryBeaconPkt =3D 0; } =20 =20 /* */ /* Init /.. Fixed HW value. Only init time. */ /* */ -void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo,= u32 Value) +void ODM_CmnInfoInit(struct dm_odm_t *dm_odm, enum odm_cmninfo_e CmnInfo, = u32 Value) { /* */ /* This section is used for init value */ @@ -819,77 +819,77 @@ void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum o= dm_cmninfo_e CmnInfo, u32 V /* Fixed ODM value. */ /* */ case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility =3D (u32)Value; + dm_odm->SupportAbility =3D (u32)Value; break; =20 case ODM_CMNINFO_PLATFORM: - pDM_Odm->SupportPlatform =3D (u8)Value; + dm_odm->SupportPlatform =3D (u8)Value; break; =20 case ODM_CMNINFO_INTERFACE: - pDM_Odm->SupportInterface =3D (u8)Value; + dm_odm->SupportInterface =3D (u8)Value; break; =20 case ODM_CMNINFO_IC_TYPE: - pDM_Odm->SupportICType =3D Value; + dm_odm->SupportICType =3D Value; break; =20 case ODM_CMNINFO_CUT_VER: - pDM_Odm->CutVersion =3D (u8)Value; + dm_odm->CutVersion =3D (u8)Value; break; =20 case ODM_CMNINFO_FAB_VER: - pDM_Odm->FabVersion =3D (u8)Value; + dm_odm->FabVersion =3D (u8)Value; break; =20 case ODM_CMNINFO_RFE_TYPE: - pDM_Odm->RFEType =3D (u8)Value; + dm_odm->RFEType =3D (u8)Value; break; =20 case ODM_CMNINFO_RF_ANTENNA_TYPE: - pDM_Odm->AntDivType =3D (u8)Value; + dm_odm->AntDivType =3D (u8)Value; break; =20 case ODM_CMNINFO_PACKAGE_TYPE: - pDM_Odm->PackageType =3D (u8)Value; + dm_odm->PackageType =3D (u8)Value; break; =20 case ODM_CMNINFO_EXT_LNA: - pDM_Odm->ExtLNA =3D (u8)Value; + dm_odm->ExtLNA =3D (u8)Value; break; =20 case ODM_CMNINFO_EXT_PA: - pDM_Odm->ExtPA =3D (u8)Value; + dm_odm->ExtPA =3D (u8)Value; break; =20 case ODM_CMNINFO_GPA: - pDM_Odm->TypeGPA =3D (enum odm_type_gpa_e)Value; + dm_odm->TypeGPA =3D (enum odm_type_gpa_e)Value; break; case ODM_CMNINFO_APA: - pDM_Odm->TypeAPA =3D (enum odm_type_apa_e)Value; + dm_odm->TypeAPA =3D (enum odm_type_apa_e)Value; break; case ODM_CMNINFO_GLNA: - pDM_Odm->TypeGLNA =3D (enum odm_type_glna_e)Value; + dm_odm->TypeGLNA =3D (enum odm_type_glna_e)Value; break; case ODM_CMNINFO_ALNA: - pDM_Odm->TypeALNA =3D (enum odm_type_alna_e)Value; + dm_odm->TypeALNA =3D (enum odm_type_alna_e)Value; break; =20 case ODM_CMNINFO_EXT_TRSW: - pDM_Odm->ExtTRSW =3D (u8)Value; + dm_odm->ExtTRSW =3D (u8)Value; break; case ODM_CMNINFO_PATCH_ID: - pDM_Odm->PatchID =3D (u8)Value; + dm_odm->PatchID =3D (u8)Value; break; case ODM_CMNINFO_BINHCT_TEST: - pDM_Odm->bInHctTest =3D (bool)Value; + dm_odm->bInHctTest =3D (bool)Value; break; case ODM_CMNINFO_BWIFI_TEST: - pDM_Odm->bWIFITest =3D (bool)Value; + dm_odm->bWIFITest =3D (bool)Value; break; =20 case ODM_CMNINFO_SMART_CONCURRENT: - pDM_Odm->bDualMacSmartConcurrent =3D (bool)Value; + dm_odm->bDualMacSmartConcurrent =3D (bool)Value; break; =20 /* To remove the compiler warning, must add an empty default statement to= handle the other values. */ @@ -901,7 +901,7 @@ void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm= _cmninfo_e CmnInfo, u32 V } =20 =20 -void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo,= void *pValue) +void ODM_CmnInfoHook(struct dm_odm_t *dm_odm, enum odm_cmninfo_e CmnInfo, = void *value) { /* */ /* Hook call by reference pointer. */ @@ -911,110 +911,110 @@ void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum= odm_cmninfo_e CmnInfo, void /* Dynamic call by reference pointer. */ /* */ case ODM_CMNINFO_MAC_PHY_MODE: - pDM_Odm->pMacPhyMode =3D pValue; + dm_odm->pMacPhyMode =3D value; break; =20 case ODM_CMNINFO_TX_UNI: - pDM_Odm->pNumTxBytesUnicast =3D pValue; + dm_odm->pNumTxBytesUnicast =3D value; break; =20 case ODM_CMNINFO_RX_UNI: - pDM_Odm->pNumRxBytesUnicast =3D pValue; + dm_odm->pNumRxBytesUnicast =3D value; break; =20 case ODM_CMNINFO_WM_MODE: - pDM_Odm->pwirelessmode =3D pValue; + dm_odm->pwirelessmode =3D value; break; =20 case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->pSecChOffset =3D pValue; + dm_odm->pSecChOffset =3D value; break; =20 case ODM_CMNINFO_SEC_MODE: - pDM_Odm->pSecurity =3D pValue; + dm_odm->pSecurity =3D value; break; =20 case ODM_CMNINFO_BW: - pDM_Odm->pBandWidth =3D pValue; + dm_odm->pBandWidth =3D value; break; =20 case ODM_CMNINFO_CHNL: - pDM_Odm->pChannel =3D pValue; + dm_odm->pChannel =3D value; break; =20 case ODM_CMNINFO_DMSP_GET_VALUE: - pDM_Odm->pbGetValueFromOtherMac =3D pValue; + dm_odm->pbGetValueFromOtherMac =3D value; break; =20 case ODM_CMNINFO_BUDDY_ADAPTOR: - pDM_Odm->pBuddyAdapter =3D pValue; + dm_odm->pBuddyAdapter =3D value; break; =20 case ODM_CMNINFO_DMSP_IS_MASTER: - pDM_Odm->pbMasterOfDMSP =3D pValue; + dm_odm->pbMasterOfDMSP =3D value; break; =20 case ODM_CMNINFO_SCAN: - pDM_Odm->pbScanInProcess =3D pValue; + dm_odm->pbScanInProcess =3D value; break; =20 case ODM_CMNINFO_POWER_SAVING: - pDM_Odm->pbPowerSaving =3D pValue; + dm_odm->pbPowerSaving =3D value; break; =20 case ODM_CMNINFO_ONE_PATH_CCA: - pDM_Odm->pOnePathCCA =3D pValue; + dm_odm->pOnePathCCA =3D value; break; =20 case ODM_CMNINFO_DRV_STOP: - pDM_Odm->pbDriverStopped =3D pValue; + dm_odm->pbDriverStopped =3D value; break; =20 case ODM_CMNINFO_PNP_IN: - pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =3D pValue; + dm_odm->pbDriverIsGoingToPnpSetPowerSleep =3D value; break; =20 case ODM_CMNINFO_INIT_ON: - pDM_Odm->pinit_adpt_in_progress =3D pValue; + dm_odm->pinit_adpt_in_progress =3D value; break; =20 case ODM_CMNINFO_ANT_TEST: - pDM_Odm->pAntennaTest =3D pValue; + dm_odm->pAntennaTest =3D value; break; =20 case ODM_CMNINFO_NET_CLOSED: - pDM_Odm->pbNet_closed =3D pValue; + dm_odm->pbNet_closed =3D value; break; =20 case ODM_CMNINFO_FORCED_RATE: - pDM_Odm->pForcedDataRate =3D pValue; + dm_odm->pForcedDataRate =3D value; break; =20 case ODM_CMNINFO_FORCED_IGI_LB: - pDM_Odm->pu1ForcedIgiLb =3D pValue; + dm_odm->pu1ForcedIgiLb =3D value; break; =20 case ODM_CMNINFO_MP_MODE: - pDM_Odm->mp_mode =3D pValue; + dm_odm->mp_mode =3D value; break; =20 /* case ODM_CMNINFO_RTSTA_AID: */ - /* pDM_Odm->pAidMap =3D (u8 *)pValue; */ + /* dm_odm->pAidMap =3D (u8 *)value; */ /* break; */ =20 /* case ODM_CMNINFO_BT_COEXIST: */ - /* pDM_Odm->BTCoexist =3D (bool *)pValue; */ + /* dm_odm->BTCoexist =3D (bool *)value; */ =20 /* case ODM_CMNINFO_STA_STATUS: */ - /* pDM_Odm->pODM_StaInfo[] =3D (PSTA_INFO_T)pValue; */ + /* dm_odm->pODM_StaInfo[] =3D (PSTA_INFO_T)value; */ /* break; */ =20 /* case ODM_CMNINFO_PHY_STATUS: */ - /* pDM_Odm->pPhyInfo =3D (ODM_PHY_INFO *)pValue; */ + /* dm_odm->pPhyInfo =3D (ODM_PHY_INFO *)value; */ /* break; */ =20 /* case ODM_CMNINFO_MAC_STATUS: */ - /* pDM_Odm->pMacInfo =3D (struct odm_mac_status_info *)pValue; */ + /* dm_odm->pMacInfo =3D (struct odm_mac_status_info *)value; */ /* break; */ /* To remove the compiler warning, must add an empty default statement to= handle the other values. */ default: @@ -1026,10 +1026,10 @@ void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum= odm_cmninfo_e CmnInfo, void =20 =20 void ODM_CmnInfoPtrArrayHook( - struct dm_odm_t *pDM_Odm, + struct dm_odm_t *dm_odm, enum odm_cmninfo_e CmnInfo, u16 Index, - void *pValue + void *value ) { /* */ @@ -1040,7 +1040,7 @@ void ODM_CmnInfoPtrArrayHook( /* Dynamic call by reference pointer. */ /* */ case ODM_CMNINFO_STA_STATUS: - pDM_Odm->pODM_StaInfo[Index] =3D (PSTA_INFO_T)pValue; + dm_odm->pODM_StaInfo[Index] =3D (PSTA_INFO_T)value; break; /* To remove the compiler warning, must add an empty default statement to= handle the other values. */ default: @@ -1054,95 +1054,95 @@ void ODM_CmnInfoPtrArrayHook( /* */ /* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ /* */ -void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value) +void ODM_CmnInfoUpdate(struct dm_odm_t *dm_odm, u32 CmnInfo, u64 Value) { /* */ /* This init variable may be changed in run time. */ /* */ switch (CmnInfo) { case ODM_CMNINFO_LINK_IN_PROGRESS: - pDM_Odm->bLinkInProcess =3D (bool)Value; + dm_odm->bLinkInProcess =3D (bool)Value; break; =20 case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility =3D (u32)Value; + dm_odm->SupportAbility =3D (u32)Value; break; =20 case ODM_CMNINFO_WIFI_DIRECT: - pDM_Odm->bWIFI_Direct =3D (bool)Value; + dm_odm->bWIFI_Direct =3D (bool)Value; break; =20 case ODM_CMNINFO_WIFI_DISPLAY: - pDM_Odm->bWIFI_Display =3D (bool)Value; + dm_odm->bWIFI_Display =3D (bool)Value; break; =20 case ODM_CMNINFO_LINK: - pDM_Odm->bLinked =3D (bool)Value; + dm_odm->bLinked =3D (bool)Value; break; =20 case ODM_CMNINFO_STATION_STATE: - pDM_Odm->bsta_state =3D (bool)Value; + dm_odm->bsta_state =3D (bool)Value; break; =20 case ODM_CMNINFO_RSSI_MIN: - pDM_Odm->RSSI_Min =3D (u8)Value; + dm_odm->RSSI_Min =3D (u8)Value; break; =20 case ODM_CMNINFO_RA_THRESHOLD_HIGH: - pDM_Odm->RateAdaptive.HighRSSIThresh =3D (u8)Value; + dm_odm->RateAdaptive.HighRSSIThresh =3D (u8)Value; break; =20 case ODM_CMNINFO_RA_THRESHOLD_LOW: - pDM_Odm->RateAdaptive.LowRSSIThresh =3D (u8)Value; + dm_odm->RateAdaptive.LowRSSIThresh =3D (u8)Value; break; /* The following is for BT HS mode and BT coexist mechanism. */ case ODM_CMNINFO_BT_ENABLED: - pDM_Odm->bBtEnabled =3D (bool)Value; + dm_odm->bBtEnabled =3D (bool)Value; break; =20 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: - pDM_Odm->bBtConnectProcess =3D (bool)Value; + dm_odm->bBtConnectProcess =3D (bool)Value; break; =20 case ODM_CMNINFO_BT_HS_RSSI: - pDM_Odm->btHsRssi =3D (u8)Value; + dm_odm->btHsRssi =3D (u8)Value; break; =20 case ODM_CMNINFO_BT_OPERATION: - pDM_Odm->bBtHsOperation =3D (bool)Value; + dm_odm->bBtHsOperation =3D (bool)Value; break; =20 case ODM_CMNINFO_BT_LIMITED_DIG: - pDM_Odm->bBtLimitedDig =3D (bool)Value; + dm_odm->bBtLimitedDig =3D (bool)Value; break; =20 case ODM_CMNINFO_BT_DISABLE_EDCA: - pDM_Odm->bBtDisableEdcaTurbo =3D (bool)Value; + dm_odm->bBtDisableEdcaTurbo =3D (bool)Value; break; =20 /* case ODM_CMNINFO_OP_MODE: - pDM_Odm->OPMode =3D (u8)Value; + dm_odm->OPMode =3D (u8)Value; break; =20 case ODM_CMNINFO_WM_MODE: - pDM_Odm->WirelessMode =3D (u8)Value; + dm_odm->WirelessMode =3D (u8)Value; break; =20 case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->SecChOffset =3D (u8)Value; + dm_odm->SecChOffset =3D (u8)Value; break; =20 case ODM_CMNINFO_SEC_MODE: - pDM_Odm->Security =3D (u8)Value; + dm_odm->Security =3D (u8)Value; break; =20 case ODM_CMNINFO_BW: - pDM_Odm->BandWidth =3D (u8)Value; + dm_odm->BandWidth =3D (u8)Value; break; =20 case ODM_CMNINFO_CHNL: - pDM_Odm->Channel =3D (u8)Value; + dm_odm->Channel =3D (u8)Value; break; */ default: diff --git a/drivers/staging/rtl8723bs/hal/odm_CfoTracking.c b/drivers/stag= ing/rtl8723bs/hal/odm_CfoTracking.c index 928c58be6c9b..000d5d44bc23 100644 --- a/drivers/staging/rtl8723bs/hal/odm_CfoTracking.c +++ b/drivers/staging/rtl8723bs/hal/odm_CfoTracking.c @@ -7,153 +7,153 @@ =20 #include "odm_precomp.h" =20 -static void odm_SetCrystalCap(void *pDM_VOID, u8 CrystalCap) +static void odm_SetCrystalCap(void *dm_void, u8 CrystalCap) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; - struct cfo_tracking *pCfoTrack =3D &pDM_Odm->DM_CfoTrack; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; + struct cfo_tracking *cfo_track =3D &dm_odm->DM_CfoTrack; =20 - if (pCfoTrack->CrystalCap =3D=3D CrystalCap) + if (cfo_track->CrystalCap =3D=3D CrystalCap) return; =20 - pCfoTrack->CrystalCap =3D CrystalCap; + cfo_track->CrystalCap =3D CrystalCap; =20 /* 0x2C[23:18] =3D 0x2C[17:12] =3D CrystalCap */ CrystalCap =3D CrystalCap & 0x3F; PHY_SetBBReg( - pDM_Odm->Adapter, + dm_odm->Adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap | (CrystalCap << 6)) ); } =20 -static u8 odm_GetDefaultCrytaltalCap(void *pDM_VOID) +static u8 odm_GetDefaultCrytaltalCap(void *dm_void) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; =20 - struct adapter *Adapter =3D pDM_Odm->Adapter; + struct adapter *Adapter =3D dm_odm->Adapter; struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); =20 return pHalData->CrystalCap & 0x3f; } =20 -static void odm_SetATCStatus(void *pDM_VOID, bool ATCStatus) +static void odm_SetATCStatus(void *dm_void, bool ATCStatus) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; - struct cfo_tracking *pCfoTrack =3D &pDM_Odm->DM_CfoTrack; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; + struct cfo_tracking *cfo_track =3D &dm_odm->DM_CfoTrack; =20 - if (pCfoTrack->bATCStatus =3D=3D ATCStatus) + if (cfo_track->bATCStatus =3D=3D ATCStatus) return; =20 PHY_SetBBReg( - pDM_Odm->Adapter, - ODM_REG(BB_ATC, pDM_Odm), - ODM_BIT(BB_ATC, pDM_Odm), + dm_odm->Adapter, + ODM_REG(BB_ATC, dm_odm), + ODM_BIT(BB_ATC, dm_odm), ATCStatus ); - pCfoTrack->bATCStatus =3D ATCStatus; + cfo_track->bATCStatus =3D ATCStatus; } =20 -static bool odm_GetATCStatus(void *pDM_VOID) +static bool odm_GetATCStatus(void *dm_void) { bool ATCStatus; - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; =20 ATCStatus =3D (bool)PHY_QueryBBReg( - pDM_Odm->Adapter, - ODM_REG(BB_ATC, pDM_Odm), - ODM_BIT(BB_ATC, pDM_Odm) + dm_odm->Adapter, + ODM_REG(BB_ATC, dm_odm), + ODM_BIT(BB_ATC, dm_odm) ); return ATCStatus; } =20 -void ODM_CfoTrackingReset(void *pDM_VOID) +void ODM_CfoTrackingReset(void *dm_void) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; - struct cfo_tracking *pCfoTrack =3D &pDM_Odm->DM_CfoTrack; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; + struct cfo_tracking *cfo_track =3D &dm_odm->DM_CfoTrack; =20 - pCfoTrack->DefXCap =3D odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bAdjust =3D true; + cfo_track->DefXCap =3D odm_GetDefaultCrytaltalCap(dm_odm); + cfo_track->bAdjust =3D true; =20 - odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); - odm_SetATCStatus(pDM_Odm, true); + odm_SetCrystalCap(dm_odm, cfo_track->DefXCap); + odm_SetATCStatus(dm_odm, true); } =20 -void ODM_CfoTrackingInit(void *pDM_VOID) +void ODM_CfoTrackingInit(void *dm_void) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; - struct cfo_tracking *pCfoTrack =3D &pDM_Odm->DM_CfoTrack; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; + struct cfo_tracking *cfo_track =3D &dm_odm->DM_CfoTrack; =20 - pCfoTrack->DefXCap =3D - pCfoTrack->CrystalCap =3D odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bATCStatus =3D odm_GetATCStatus(pDM_Odm); - pCfoTrack->bAdjust =3D true; + cfo_track->DefXCap =3D + cfo_track->CrystalCap =3D odm_GetDefaultCrytaltalCap(dm_odm); + cfo_track->bATCStatus =3D odm_GetATCStatus(dm_odm); + cfo_track->bAdjust =3D true; } =20 -void ODM_CfoTracking(void *pDM_VOID) +void ODM_CfoTracking(void *dm_void) { - struct dm_odm_t *pDM_Odm =3D (struct dm_odm_t *)pDM_VOID; - struct cfo_tracking *pCfoTrack =3D &pDM_Odm->DM_CfoTrack; + struct dm_odm_t *dm_odm =3D (struct dm_odm_t *)dm_void; + struct cfo_tracking *cfo_track =3D &dm_odm->DM_CfoTrack; int CFO_kHz_A, CFO_ave =3D 0; int CFO_ave_diff; - int CrystalCap =3D (int)pCfoTrack->CrystalCap; + int CrystalCap =3D (int)cfo_track->CrystalCap; u8 Adjust_Xtal =3D 1; =20 /* 4 Support ability */ - if (!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) { + if (!(dm_odm->SupportAbility & ODM_BB_CFO_TRACKING)) { return; } =20 - if (!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) { + if (!dm_odm->bLinked || !dm_odm->bOneEntryOnly) { /* 4 No link or more than one entry */ - ODM_CfoTrackingReset(pDM_Odm); + ODM_CfoTrackingReset(dm_odm); } else { /* 3 1. CFO Tracking */ /* 4 1.1 No new packet */ - if (pCfoTrack->packetCount =3D=3D pCfoTrack->packetCount_pre) { + if (cfo_track->packetCount =3D=3D cfo_track->packetCount_pre) { return; } - pCfoTrack->packetCount_pre =3D pCfoTrack->packetCount; + cfo_track->packetCount_pre =3D cfo_track->packetCount; =20 /* 4 1.2 Calculate CFO */ - CFO_kHz_A =3D (int)(pCfoTrack->CFO_tail[0] * 3125) / 1280; + CFO_kHz_A =3D (int)(cfo_track->CFO_tail[0] * 3125) / 1280; =20 CFO_ave =3D CFO_kHz_A; =20 /* 4 1.3 Avoid abnormal large CFO */ CFO_ave_diff =3D - (pCfoTrack->CFO_ave_pre >=3D CFO_ave) ? - (pCfoTrack->CFO_ave_pre-CFO_ave) : - (CFO_ave-pCfoTrack->CFO_ave_pre); + (cfo_track->CFO_ave_pre >=3D CFO_ave) ? + (cfo_track->CFO_ave_pre-CFO_ave) : + (CFO_ave-cfo_track->CFO_ave_pre); =20 if ( CFO_ave_diff > 20 && - pCfoTrack->largeCFOHit =3D=3D 0 && - !pCfoTrack->bAdjust + cfo_track->largeCFOHit =3D=3D 0 && + !cfo_track->bAdjust ) { - pCfoTrack->largeCFOHit =3D 1; + cfo_track->largeCFOHit =3D 1; return; } else - pCfoTrack->largeCFOHit =3D 0; - pCfoTrack->CFO_ave_pre =3D CFO_ave; + cfo_track->largeCFOHit =3D 0; + cfo_track->CFO_ave_pre =3D CFO_ave; =20 /* 4 1.4 Dynamic Xtal threshold */ - if (pCfoTrack->bAdjust =3D=3D false) { + if (cfo_track->bAdjust =3D=3D false) { if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) - pCfoTrack->bAdjust =3D true; + cfo_track->bAdjust =3D true; } else { if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) - pCfoTrack->bAdjust =3D false; + cfo_track->bAdjust =3D false; } =20 /* 4 1.5 BT case: Disable CFO tracking */ - if (pDM_Odm->bBtEnabled) { - pCfoTrack->bAdjust =3D false; - odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); + if (dm_odm->bBtEnabled) { + cfo_track->bAdjust =3D false; + odm_SetCrystalCap(dm_odm, cfo_track->DefXCap); } =20 /* 4 1.6 Big jump */ - if (pCfoTrack->bAdjust) { + if (cfo_track->bAdjust) { if (CFO_ave > CFO_TH_XTAL_LOW) Adjust_Xtal =3D Adjust_Xtal+((CFO_ave-CFO_TH_XTAL_LOW)>>2); else if (CFO_ave < (-CFO_TH_XTAL_LOW)) @@ -161,7 +161,7 @@ void ODM_CfoTracking(void *pDM_VOID) } =20 /* 4 1.7 Adjust Crystal Cap. */ - if (pCfoTrack->bAdjust) { + if (cfo_track->bAdjust) { if (CFO_ave > CFO_TH_XTAL_LOW) CrystalCap =3D CrystalCap + Adjust_Xtal; else if (CFO_ave < (-CFO_TH_XTAL_LOW)) @@ -172,14 +172,14 @@ void ODM_CfoTracking(void *pDM_VOID) else if (CrystalCap < 0) CrystalCap =3D 0; =20 - odm_SetCrystalCap(pDM_Odm, (u8)CrystalCap); + odm_SetCrystalCap(dm_odm, (u8)CrystalCap); } =20 /* 3 2. Dynamic ATC switch */ if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) { - odm_SetATCStatus(pDM_Odm, false); + odm_SetATCStatus(dm_odm, false); } else { - odm_SetATCStatus(pDM_Odm, true); + odm_SetATCStatus(dm_odm, true); } } } --=20 2.34.1