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[195.38.113.151]) by smtp.gmail.com with ESMTPSA id p2-20020a170906604200b0072b1cb2818csm5291203ejj.158.2022.08.21.14.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 14:10:08 -0700 (PDT) Sender: Ingo Molnar Date: Sun, 21 Aug 2022 23:10:06 +0200 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Peter Zijlstra , Borislav Petkov , Andrew Morton , Marc Zyngier Subject: [GIT PULL] IRQ fixes Message-ID: MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Linus, Please pull the latest irq/urgent git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-urgent-202= 2-08-21 # HEAD: 57646d6769f13f9484ffc6869c493e25a6568073 Merge tag 'irqchip-fixe= s-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms= into irq/urgent Misc irqchip fixes: LoongArch driver fixes and a Hyper-V IOMMU fix. Thanks, Ingo ------------------> Christophe JAILLET (1): irqchip/loongson-liointc: Fix an error handling path in liointc_init() Huacai Chen (3): irqchip/loongson-eiointc: Fix irq affinity setting irqchip/loongson-eiointc: Fix a build warning irqchip/loongson-pch-pic: Move find_pch_pic() into CONFIG_ACPI Marc Zyngier (1): irqchip/loongarch: Fix irq_domain_alloc_fwnode() abuse Michael Kelley (1): iommu/hyper-v: Use helper instead of directly accessing affinity arch/loongarch/include/asm/irq.h | 1 - drivers/iommu/hyperv-iommu.c | 4 +--- drivers/irqchip/irq-loongarch-cpu.c | 2 +- drivers/irqchip/irq-loongson-eiointc.c | 13 +++++++---- drivers/irqchip/irq-loongson-liointc.c | 4 ++-- drivers/irqchip/irq-loongson-pch-msi.c | 2 +- drivers/irqchip/irq-loongson-pch-pic.c | 40 +++++++++++++++++-------------= ---- 7 files changed, 34 insertions(+), 32 deletions(-) diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/= irq.h index 4b130199ceae..d06d4542b634 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -81,7 +81,6 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS]; #define GSI_MIN_PCH_IRQ LOONGSON_PCH_IRQ_BASE #define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1) =20 -extern int find_pch_pic(u32 gsi); struct acpi_madt_lio_pic; struct acpi_madt_eio_pic; struct acpi_madt_ht_pic; diff --git a/drivers/iommu/hyperv-iommu.c b/drivers/iommu/hyperv-iommu.c index 51bd66a45a11..e190bb8c225c 100644 --- a/drivers/iommu/hyperv-iommu.c +++ b/drivers/iommu/hyperv-iommu.c @@ -68,7 +68,6 @@ static int hyperv_irq_remapping_alloc(struct irq_domain *= domain, { struct irq_alloc_info *info =3D arg; struct irq_data *irq_data; - struct irq_desc *desc; int ret =3D 0; =20 if (!info || info->type !=3D X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) @@ -90,8 +89,7 @@ static int hyperv_irq_remapping_alloc(struct irq_domain *= domain, * Hypver-V IO APIC irq affinity should be in the scope of * ioapic_max_cpumask because no irq remapping support. */ - desc =3D irq_data_to_desc(irq_data); - cpumask_copy(desc->irq_common_data.affinity, &ioapic_max_cpumask); + irq_data_update_affinity(irq_data, &ioapic_max_cpumask); =20 return 0; } diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loon= garch-cpu.c index 327f3ab62c03..741612ba6a52 100644 --- a/drivers/irqchip/irq-loongarch-cpu.c +++ b/drivers/irqchip/irq-loongarch-cpu.c @@ -129,7 +129,7 @@ static int __init cpuintc_acpi_init(union acpi_subtable= _headers *header, clear_csr_ecfg(ECFG0_IM); clear_csr_estat(ESTATF_IP); =20 - cpuintc_handle =3D irq_domain_alloc_fwnode(NULL); + cpuintc_handle =3D irq_domain_alloc_named_fwnode("CPUINTC"); irq_domain =3D irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM, &loongarch_cpu_intc_irq_domain_ops, NULL); =20 diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index 80d8ca6f2d46..16e9af8d8b1e 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -111,11 +111,15 @@ static int eiointc_set_irq_affinity(struct irq_data *= d, const struct cpumask *af regaddr =3D EIOINTC_REG_ENABLE + ((vector >> 5) << 2); =20 /* Mask target vector */ - csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0); + csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), + 0x0, priv->node * CORES_PER_EIO_NODE); + /* Set route for target vector */ eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map); + /* Unmask target vector */ - csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0); + csr_any_send(regaddr, EIOINTC_ALL_ENABLE, + 0x0, priv->node * CORES_PER_EIO_NODE); =20 irq_data_update_effective_affinity(d, cpumask_of(cpu)); =20 @@ -286,7 +290,7 @@ static void acpi_set_vec_parent(int node, struct irq_do= main *parent, struct acpi } } =20 -struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group = *vec_group) +static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector= _group *vec_group) { int i; =20 @@ -344,7 +348,8 @@ int __init eiointc_acpi_init(struct irq_domain *parent, if (!priv) return -ENOMEM; =20 - priv->domain_handle =3D irq_domain_alloc_fwnode((phys_addr_t *)acpi_eioin= tc); + priv->domain_handle =3D irq_domain_alloc_named_id_fwnode("EIOPIC", + acpi_eiointc->node); if (!priv->domain_handle) { pr_err("Unable to allocate domain handle\n"); goto out_free_priv; diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index c4f3c886ad61..0da8716f8f24 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -207,7 +207,7 @@ static int liointc_init(phys_addr_t addr, unsigned long= size, int revision, "reg-names", core_reg_names[i]); =20 if (index < 0) - return -EINVAL; + goto out_iounmap; =20 priv->core_isr[i] =3D of_iomap(node, index); } @@ -360,7 +360,7 @@ int __init liointc_acpi_init(struct irq_domain *parent,= struct acpi_madt_lio_pic parent_irq[0] =3D irq_create_mapping(parent, acpi_liointc->cascade[0]); parent_irq[1] =3D irq_create_mapping(parent, acpi_liointc->cascade[1]); =20 - domain_handle =3D irq_domain_alloc_fwnode((phys_addr_t *)acpi_liointc); + domain_handle =3D irq_domain_alloc_fwnode(&acpi_liointc->address); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-l= oongson-pch-msi.c index d0e8551bebfa..a72ede90ffc6 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -282,7 +282,7 @@ int __init pch_msi_acpi_init(struct irq_domain *parent, int ret; struct fwnode_handle *domain_handle; =20 - domain_handle =3D irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi); + domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address); ret =3D pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start, acpi_pchmsi->count, parent, domain_handle); if (ret < 0) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index b6f1392964b1..c01b9c257005 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -48,25 +48,6 @@ static struct pch_pic *pch_pic_priv[MAX_IO_PICS]; =20 struct fwnode_handle *pch_pic_handle[MAX_IO_PICS]; =20 -int find_pch_pic(u32 gsi) -{ - int i; - - /* Find the PCH_PIC that manages this GSI. */ - for (i =3D 0; i < MAX_IO_PICS; i++) { - struct pch_pic *priv =3D pch_pic_priv[i]; - - if (!priv) - return -1; - - if (gsi >=3D priv->gsi_base && gsi < (priv->gsi_base + priv->vec_count)) - return i; - } - - pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi); - return -1; -} - static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit) { u32 reg; @@ -325,6 +306,25 @@ IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_p= ic_of_init); #endif =20 #ifdef CONFIG_ACPI +int find_pch_pic(u32 gsi) +{ + int i; + + /* Find the PCH_PIC that manages this GSI. */ + for (i =3D 0; i < MAX_IO_PICS; i++) { + struct pch_pic *priv =3D pch_pic_priv[i]; + + if (!priv) + return -1; + + if (gsi >=3D priv->gsi_base && gsi < (priv->gsi_base + priv->vec_count)) + return i; + } + + pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi); + return -1; +} + static int __init pch_lpc_parse_madt(union acpi_subtable_headers *header, const unsigned long end) @@ -349,7 +349,7 @@ int __init pch_pic_acpi_init(struct irq_domain *parent, =20 vec_base =3D acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ; =20 - domain_handle =3D irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic); + domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchpic->address); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM;