From nobody Sat Sep 21 11:48:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52EFFC38A2D for ; Wed, 26 Oct 2022 00:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231679AbiJZA5P (ORCPT ); Tue, 25 Oct 2022 20:57:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbiJZA5N (ORCPT ); Tue, 25 Oct 2022 20:57:13 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50741B56F5; Tue, 25 Oct 2022 17:57:11 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.94.2) (envelope-from ) id 1onUjB-0002Yp-PL; Wed, 26 Oct 2022 02:57:06 +0200 Date: Wed, 26 Oct 2022 01:56:58 +0100 From: Daniel Golle To: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Matthias Brugger Cc: Fabien Parent , Zhi Mao , Sam Shih Subject: [PATCH] pwm: mediatek: always use bus clock for PWM on MT7622 Message-ID: MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to MT7622 Reference Manual for Development Board v1.0 the PWM unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register at offset 0x210 just like other modern MediaTek ARM64 SoCs. And also MT7622 sets that register to 0x00000001 on reset which is described as 'Select 26M fix CLK as BCLK' in the datasheet. Hence set has_ck_26m_sel to true also for MT7622 which results in the driver writing 0 to the PWM_CK_26M_SEL register which is described as 'Select bus CLK as BCLK'. Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock") Signed-off-by: Daniel Golle Acked-by: Uwe Kleine-K=C3=B6nig Reviewed-by: AngeloGioacchino Del Regno --- drivers/pwm/pwm-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 2219cba033e348..5b5eeaff35da67 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -296,7 +296,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_dat= a =3D { static const struct pwm_mediatek_of_data mt7622_pwm_data =3D { .num_pwms =3D 6, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D false, + .has_ck_26m_sel =3D true, }; =20 static const struct pwm_mediatek_of_data mt7623_pwm_data =3D { --=20 2.38.1