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Wed, 18 Oct 2023 23:18:54 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263%5]) with mapi id 15.20.6907.021; Wed, 18 Oct 2023 23:18:54 +0000 From: Inochi Amaoto To: Chao Wei , Chen Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Jisheng Zhang , Inochi Amaoto , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc Date: Thu, 19 Oct 2023 07:18:51 +0800 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: Content-Transfer-Encoding: quoted-printable X-TMN: [3uzAu3jYS2COcaHVvtN6QcvsWi+5/1Lfo1W8zkEPw4c=] X-ClientProxiedBy: BYAPR07CA0084.namprd07.prod.outlook.com (2603:10b6:a03:12b::25) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231018231855.28472-4-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|DM4PR20MB5087:EE_ X-MS-Office365-Filtering-Correlation-Id: e38dc7f4-3002-43d4-4028-08dbd03098d0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" As CV180x and CV181x have the identical layouts, it is OK to use the cv1800b basic device tree for the whole series. For CV1800B soc specific compatible, just move them out of the common file. Signed-off-by: Inochi Amaoto Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 ++--------------------- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 120 ++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 112 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index df40e87ee063..165e9e320a8c 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,121 +3,16 @@ * Copyright (C) 2023 Jisheng Zhang */ -#include +#include "cv18xx.dtsi" / { compatible =3D "sophgo,cv1800b"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - cpus: cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - timebase-frequency =3D <25000000>; - - cpu0: cpu@0 { - compatible =3D "thead,c906", "riscv"; - device_type =3D "cpu"; - reg =3D <0>; - d-cache-block-size =3D <64>; - d-cache-sets =3D <512>; - d-cache-size =3D <65536>; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <32768>; - mmu-type =3D "riscv,sv39"; - riscv,isa =3D "rv64imafdc"; - riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - }; - - osc: oscillator { - compatible =3D "fixed-clock"; - clock-output-names =3D "osc_25m"; - #clock-cells =3D <0>; - }; - - soc { - compatible =3D "simple-bus"; - interrupt-parent =3D <&plic>; - #address-cells =3D <1>; - #size-cells =3D <1>; - dma-noncoherent; - ranges; - - uart0: serial@4140000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x04140000 0x100>; - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&osc>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart1: serial@4150000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x04150000 0x100>; - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&osc>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart2: serial@4160000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x04160000 0x100>; - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&osc>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart3: serial@4170000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x04170000 0x100>; - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&osc>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart4: serial@41c0000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x041c0000 0x100>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&osc>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; +}; - plic: interrupt-controller@70000000 { - compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; - reg =3D <0x70000000 0x4000000>; - interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <2>; - riscv,ndev =3D <101>; - }; +&plic { + compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; +}; - clint: timer@74000000 { - compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; - reg =3D <0x74000000 0x10000>; - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; - }; - }; +&clint { + compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv18xx.dtsi new file mode 100644 index 000000000000..55d4bc84faa0 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_25m"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04140000 0x100>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@4150000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04150000 0x100>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@4160000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04160000 0x100>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@4170000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04170000 0x100>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@41c0000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x041c0000 0x100>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + plic: interrupt-controller@70000000 { + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; -- 2.42.0