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b=K7OhW7BMym8GxSvUswYoV5CIXuAs/gXG1rs+xCn5mrVmHOF3ZYoMRZqH0967WM+hUMkjAedEZeuBjNwQZbkB8SUIwwC3tkKOoQ/4EzDx5mrcqKNS0eSurJicxtbzA3K3nj4xEU94IkESCxqf6O6rYjq3TBmYiLvYAEK9UCKn0/Y= Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by AS8PR04MB8785.eurprd04.prod.outlook.com (2603:10a6:20b:42c::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6678.31; Thu, 24 Aug 2023 12:52:58 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::2b3:d8de:95c8:b28b]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::2b3:d8de:95c8:b28b%3]) with mapi id 15.20.6699.027; Thu, 24 Aug 2023 12:52:58 +0000 From: Peng Fan To: Sudeep Holla , Linus Walleij CC: "Peng Fan (OSS)" , "oleksii_moisieiev@epam.com" , Aisheng Dong , "festevam@gmail.com" , Jacky Bai , "s.hauer@pengutronix.de" , "shawnguo@kernel.org" , "kernel@pengutronix.de" , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" Subject: RE: [RFC] scmi: pinctrl: support i.MX9 Thread-Topic: [RFC] scmi: pinctrl: support i.MX9 Thread-Index: AQHZ1ljQGymVJC/R70ObhTQ99JrC7K/5IV8AgAAj2ICAACCTYA== Date: Thu, 24 Aug 2023 12:52:58 +0000 Message-ID: References: <20230824070611.3335107-1-peng.fan@oss.nxp.com> <20230824105137.xqkwi4xvmjoidexh@bogus> In-Reply-To: <20230824105137.xqkwi4xvmjoidexh@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a6e14eb-6d05-40c6-75bf-08dba4a10b36 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2023 12:52:58.7582 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sBwJnoPzqc7PLlje6HS0dMbQd5fMJj7yIkbGG+EvEuQt6SDLb/CvzpBo7S3ctfbk/yn4LDGY5lwZSG+JU9sKlQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8785 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sudeep, > Subject: Re: [RFC] scmi: pinctrl: support i.MX9 >=20 > Hi Linus, >=20 > Thanks a lot for the quick response. >=20 > On Thu, Aug 24, 2023 at 10:43:20AM +0200, Linus Walleij wrote: > > On Thu, Aug 24, 2023 at 9:01=E2=80=AFAM Peng Fan (OSS) > wrote: > > > > > This patch is just to introduce i.MX support to see whether people > > > have comments for the design. > > > > Very interesting! > > > > > The binding format: > > > > > > dts: > > > pinctrl_uart1: uart1grp { > > > fsl,pins =3D < > > > MX93_PAD_UART1_RXD__LPUART1_RX = 0x31e > > > MX93_PAD_UART1_TXD__LPUART1_TX = 0x31e > > > >; > > > }; > > > > > > i.MX pinctrl not use generic pinconf, this has been agreeed by > > > maintainers before. > > > > Yes, it has historical reasons. > > >=20 > Good to know. >=20 > > > So after moving to SCMI, we will still keep the same binding format, > > > and i.MX SCMI firmware also use same format when configure > > > registers. So we need to use i.MX specific dt_node_to_map function. > > > > I thought the idea with SCMI was to abstract and hide the > > characteristics of the underlying hardware. I.e. the firmware is to > > present groups and functions and generic config options and then the > driver will use these. > > >=20 > Correct. >=20 > > This patch, it seems, creates a hybrid between the old freescale > > driver and the SCMI firmware communication link where the SCMI is just > > a transport mechanism to something inside SCMI that poke the same > > registers that userspace could poke, if it could only access these > > registers. > > > > I.e using SCMI on this platform isn't creating any abstraction of the > > pin control hardware, it is merely making things more complex and also > > slower bymaking the registers only accessible from this SCMI link. > > >=20 > Agreed. >=20 > I don't have much knowledge on generic pinmux conf and suggested Peng to > post the RFC to start the discussion instead of getting blocked by me dur= ing > some internal/private discussions as the main intention for him was > upstreaming the changes. I am against the idea of mixing platform specific > changes the way it is done here but since I didn't have much knowledge on > pinmux conf to suggest/provide any useful feedback I suggested to trigger > this discussion. To use generic pinconf, we still need to extend to use OEM type, our scmi f= irmware will not support saying bias/pull-up and etc config type, so just as below,= we add: diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-ge= neric.c index 365c4b0ca465..a71721cd321d 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -186,6 +186,16 @@ static const struct pinconf_generic_params dt_params[]= =3D { { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, + { "nxp-mux", PIN_CONFIG_NXP_MUX, 0 }, + { "nxp-conf", PIN_CONFIG_NXP_CONF, 0 }, + { "nxp-daisy-id", PIN_CONFIG_NXP_DAISY_ID, 0 }, + { "nxp-daisy-val", PIN_CONFIG_NXP_DAISY_VAL, 0 }, }; And in dts: + pinctrl_uart1: uart1grp { + txd { + pins =3D "uart1txd"; + nxp-mux =3D <0x0>; + nxp-conf =3D <0x31e>; + }; + + rxd { + pins =3D "uart1rxd"; + nxp-mux =3D <0x0>; + nxp-conf =3D <0x31e>; + }; + }; But the upper will make device tree diverge w/o scmi, because we need support both for i.MX95. I still prefer to use freescale current binding format which would make dts reusable w/o scmi. Thanks, Peng. >=20 > > But I could have misunderstood it, so please correct me! >=20 > +1 >=20 > -- > Regards, > Sudeep