From nobody Tue Sep 29 02:01:53 2026 Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 435A24746D5 for ; Thu, 13 Aug 2026 13:06:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=18.132.163.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786626381; cv=none; b=RyZF4rUxfHkvIJtleOCSPxfodzXaU4Lp6ED9ZVAy1hQYq8OfaGKe+ysgKDPCpglTBp658casX8eUvjavxH3k+BV/si14vABNwam7sKDAMEVw78fWAQujveq8FcmVaQzl2jnDlUdCBnWclt/GQI0Qbz6jMSGYsBvo/V6DLTOj4uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786626381; c=relaxed/simple; bh=iKlsdRlRYxYc1v0CKgJEbY5DgTP+wXoI6/8725kvTKc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=tMkKvEOf+T78QwF0URM1t4QLGsHGn0QDCuP+w6EUQ/vONSRXGhPkbE0tsykPCv06hnu2yc4W8uKu0CMtNm/PpfkD8ed5EEqHbvbyS1ePw6fsj0d+EsTHF1YgErXLLCxeHcMB0qxNHxT6obVrRA40p+ocPNL/JH87Dco3019zC60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com; spf=pass smtp.mailfrom=uniontech.com; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b=G3IWzoV5; arc=none smtp.client-ip=18.132.163.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=uniontech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b="G3IWzoV5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=uniontech.com; s=onoh2408; t=1786626372; bh=nJ3DjTBgFoGEsLV5b+erjzQOcSw5I5/IyYlcPZdcDEs=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=G3IWzoV5EOO0MqltH/BYxWOl13Xpx0sJwqdt1GpCV4BVrw4hySa0YYNBZ2BXUVwdU QxuzF8q4utk3j9yZ9I7u4adgspLREqajTWtY47Bdc1POIwlVeKL2DPxgq5/qvzKYWq 6gthPwxL1seqKMCE6ykH3ZsLJRzOWlwB593lppuk= X-QQ-mid: esmtpgz12t1786626355t9ca26cba X-QQ-Originating-IP: dHhI7VBaezRAp4X4gI1x1FX2IMsrpI09Qjr/PigbalE= Received: from PEN202512010004 ( [113.57.152.160]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 13 Aug 2026 21:05:53 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 1 X-BIZMAIL-ID: 588101152483150386 EX-QQ-RecipientCnt: 12 From: raoxu To: vkoul@kernel.org Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, neil.armstrong@linaro.org, andre.przywara@arm.com, marco.crivellari@suse.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, raoxu@uniontech.com Subject: [PATCH v2] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup Date: Thu, 13 Aug 2026 21:05:42 +0800 Message-ID: X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:uniontech.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: M83iEva+1QDB8QBhMvdtyv3tef5H5W8if+j161KRElUp61kZJTkFaqgm usDsHmIEOwveD0/Tsh/JkVXHzWC9dJUTaniTlLPXTrFww0HwlfU73QNq6xvwI3uf8oIMopK Cl8wVkCY+vrEsko0AWftCw1pq+LdCqbOUa8t9ibp6m1qzXfDPEqF+lLGr0eIV0K3PN5BVoL ZWYTs6rphagze0Qg5aZ5YbjD1F2rQ+dBsLLd3SM35BWszuwqI6p8xN9O2UIIE9S0zqRx2Im YC2VTAm4WecwyW/Gc+CX4gq38qF1dXiodKWsAA56H4k1jPKrFCsR/YPrnHQBvL17CaegrOP qS3hVFlZaDHUFG96htfidvkzE3z28D4xNhgDY1Uk6AyWst/zLQFLvAu7yvND+8szZLAYV8P 3XPaGRNBwNa3mA5KSSajT9OwKHQZ19StzX6kl0iOHkKT0KL8dD5H8BwPQQbg17LM4Gb/pBy rLb+khKXeQQWwORG3RDEz8z0b1IITMX4X9/pvyH3a2o1SWAZHoSP+kKEdMXQoGMhTMICPkx Y2j6YH11n18Q6bannwq+/uJ6ptvYdAX2nya/X3mbtcFRxUrWkFgw5SsxIhtUQP9DzYhW2Aj nRA3aylDdVN6SkyAm/xj3tSz+UmJ+h3jzzrHeedTjt9F5TY4PLlz1y6KRdE3Rqb6A/8j8CF FZVtYI1W64a5rZOkVfvlodQO9cjRl0vEP9jrYDbelWH2WOTxXh+0EvZkEXKskqBvfx26lY5 i9GZP291XCfR9Bj8d2lXlKw4UU2u886utoUx84YbFI54UftrUpLEg/72+Q2bNZOTthYbCOy IPRZQqP8Z3raVrPEtwnm3Q8qKOtnqkNqOtR3w4FIjdMO8q/yUBxtjpwg7/5KfV+kOSQJbOI eIsc0dBVTFEpLmCO8z5mt+qPbNwY5zds/Rnv/jzGLsjaBtTnAX6EmzxRzp8SSaWzokCb03+ BRI1vNWhDSMtXsV22LZEdPS9zePVrvlhy6c5kYFfXOKsGdRwgZ83W/z5r/bpykTjr31E2lr 7QU4rkAnzzQ7wvb2s+7ZzmLjpVJKPCKPE0/2YN042nnBKvQhEnwGa0BVVFjeMv7eFUcKLq5 Q== X-QQ-XMRINFO: OWPUhxQsoeAVwkVaQIEGSKwwgKCxK/fD5g== X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" From: Xu Rao sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs PHY2 SIDDQ setup while initializing another PHY. However, after updating PHY2's PMU register it disables the clk2 pointer from the PHY currently being initialized instead. Only PHY2 on H616 has a clk2 clock. No other PHY on H616 has a clk2 clock, so phy->clk2 is NULL in this path and disabling it is a no-op. This is why disabling the wrong clock did not cause an additional functional failure. The temporary phy2->clk2 enable therefore remains unmatched, leaking a clock enable reference each time this path is executed. Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access. Fixes: b45c6d80325b ("phy: sun4i-usb: Introduce port2 SIDDQ quirk") Reviewed-by: Andre Przywara Signed-off-by: Xu Rao --- Changes in v2: - Explain why disabling phy->clk2 did not cause additional harm: no other PHY on H616 has clk2, so phy->clk2 is NULL and the operation is a no-op. - Clarify that the concrete issue is the unmatched PHY2 clk2 enable. - Add the Fixes tag and Andre's Reviewed-by. drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index e2fbf8ccf99e..839856c09e30 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -318,7 +318,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, phy2->pmu + REG_HCI_PHY_CTL); } - clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy2->clk2); } if (phy->pmu && data->cfg->hci_phy_ctl_clear) { -- 2.50.1