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Fri, 03 Jan 2025 00:49:06 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: qin shaoqing Date: Fri, 3 Jan 2025 16:48:56 +0800 Message-ID: Subject: [PATCH] riscv: dts: Add the device tree of the XiangShan platform's nanhu soc To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, wangran@bosc.ac.cn Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds the device tree support for the XiangShan platform's nanhu = soc Signed-off-by: qinshaoqing --- arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/xiangshan/Makefile | 2 + arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts | 226 ++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 arch/riscv/boot/dts/xiangshan/Makefile create mode 100644 arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index f51bb24bc84c..89c80fd493fb 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -80,4 +80,9 @@ config SOC_CANAAN_K210 help This enables support for Canaan Kendryte K210 SoC platform hardware. +config SOC_XIANGSHAN + bool "XiangShan SoCs" + help + This enables support for XiangShan SoC platform hardware + endmenu # "SoC selection" diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index fdae05bbf556..43a79cc9dd7c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -7,5 +7,6 @@ subdir-y +=3D sifive subdir-y +=3D sophgo subdir-y +=3D starfive subdir-y +=3D thead +subdir-y +=3D xiangshan obj-$(CONFIG_BUILTIN_DTB) :=3D $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOU= RCE)) diff --git a/arch/riscv/boot/dts/xiangshan/Makefile b/arch/riscv/boot/dts/xiangshan/Makefile new file mode 100644 index 000000000000..41e585490a97 --- /dev/null +++ b/arch/riscv/boot/dts/xiangshan/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_XIANGSHAN) +=3D nanhu-v3a.dtb diff --git a/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts new file mode 100644 index 000000000000..560de7c7f22e --- /dev/null +++ b/arch/riscv/boot/dts/xiangshan/nanhu-v3a.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023-2024 BOSC */ + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "bosc,nanhu-v3a"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <24000000>; + + cpu0: cpu@0 { + compatible =3D "bosc,nanhu-v3a", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <16384>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <16384>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <0x0>; + + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "bosc,nanhu-v3a", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <16384>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <16384>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <0x1>; + + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + clkc: misc_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "clkc"; + clock-frequency =3D <100000000>; + }; + + sdhci_clock: sdhci_clck { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "sdhci_clock"; + clock-frequency =3D <25000000>; + }; + + i2c0_clock: i2c0_clck { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "i2c0_clock"; + clock-frequency =3D <100000000>; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "bosc,nanhu-v3a-soc", "simple-bus"; + ranges; + + clint0: clint@38000000 { + compatible =3D "riscv,clint0"; + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_i= ntc 7>; + reg =3D <0x0 0x38000000 0x0 0x10000>; + reg-names =3D "control"; + clock-frequency-mhz =3D <10>; + }; + + plic: interrupt-controller@3c000000 { + #interrupt-cells =3D <1>; + compatible =3D "riscv,plic0"; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 0xb &cpu0_intc 0x9 &cpu1_intc 0xb &cpu1_intc 0x9>; + reg =3D <0 0x3c000000 0 0x4000000>; + reg-names =3D "control"; + riscv,max-priority =3D <7>; + riscv,ndev =3D <128>; + }; + + ethernet0: ethernet@190000 { + compatible =3D "st,stm32-dwmac", "snps,dwmac-3.50a"; + reg =3D <0 0x190000 0 0x10000>; + reg-names =3D "stmmaceth"; + interrupt-parent =3D <&plic>; + interrupts =3D <76 75 74>; + interrupt-names =3D "eth_lpi", "macirq", "eth_wake_irq"; + clock-names =3D "stmmaceth"; + clocks =3D <&clkc>; + snps,pbl =3D <2>; + snps,mixed-burst; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy0>; + mdio0: mdio { + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + compatible =3D "snps,dwmac-mdio"; + phy0: phy@0 { + phyaddr =3D <0x0>; + compatible =3D "marvell,88E1510"; + device_type =3D "ethernet-phy"; + reg =3D <0x0>; + }; + phy1: phy@1 { + phyaddr =3D <0x1>; + compatible =3D "marvell,88E1510"; + device_type =3D "ethernet-phy"; + reg =3D <0x1>; + }; + }; + }; + + ethernet1: ethernet@1a0000 { + compatible =3D "st,stm32-dwmac", "snps,dwmac-3.50a"; + reg =3D <0 0x1a0000 0 0x10000>; + reg-names =3D "stmmaceth1"; + interrupt-parent =3D <&plic>; + interrupts =3D <73 72 71>; + interrupt-names =3D "eth_lpi", "macirq", "eth_wake_irq"; + clock-names =3D "stmmaceth"; + clocks =3D <&clkc>; + snps,pbl =3D <2>; + snps,mixed-burst; + phy-mode =3D "rgmii"; + fixed-link{ + speed =3D <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + + sdhci2: sdhci@1200000 { + compatible =3D "snps,dwcmshc-sdhci"; + reg =3D <0 0x1200000 0 0x20000>; + interrupt-parent =3D <&plic>; + interrupts =3D <77 78>; + clocks =3D <&sdhci_clock>; + clock-names =3D "core"; + no-1-8-v; + disable-wp; + bus-width =3D <4>; + max_req_size =3D <4096>; + status =3D "okay"; + }; + + i2c@70000 { + compatible =3D "snps,designware-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x70000 0x0 0x10000>; + interrupts =3D <66>; + interrupt-parent =3D <&plic>; + clock-frequency =3D <100000>; + clocks =3D <&i2c0_clock>; + status =3D "okay"; + }; + + i2c@80000 { + compatible =3D "snps,designware-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x80000 0x0 0x10000>; + interrupts =3D <65>; + interrupt-parent =3D <&plic>; + clock-frequency =3D <100000>; + clocks =3D <&i2c0_clock>; + status =3D "okay"; + }; + + uart0: serial@50000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x50000 0x0 0x10000>; + reg-shift =3D <0x02>; + reg-io-width =3D <0x04>; + interrupt-parent =3D <&plic>; + interrupts =3D <68>; + clock-frequency =3D <100000000>; + status =3D "okay"; + }; + }; + + memory: memory@100000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + bootargs =3D "console=3DttyS0,115200 earlycon"; + stdout-path =3D "serial0:115200n8"; + }; +}; -- 2.43.0