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charset="utf-8" From 9b2f563e1286c960ad81bc78ec811029ffb2f57a Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Sat, 29 Apr 2023 19:03:53 +0530 Subject: [PATCH] Add a device tree file for Emtop SOM IMX8MM Added dts for describing the Emtop SOM-IMX8MM Signed-off-by: Himanshu Bhavani diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 198fff3731ae..8f281c753e5a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-verdin-nonwifi-yavia.d= tb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-emtop.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-bsh-smm-s2pro.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop.dts b/arch/arm64/bo= ot/dts/freescale/imx8mm-emtop.dts new file mode 100644 index 000000000000..5238a3b5f4cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + model =3D "FSL i.MX8MM Emtop SOM"; + compatible =3D "fsl,imx8mm-emtop", "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + stdout-path =3D &uart2; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + sys { + label =3D "sys"; + gpios =3D <&gpio3 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&uart2 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pmic@25 { + reg =3D <0x25>; + compatible =3D "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + + buck1: BUCK1 { + regulator-compatible =3D "BUCK1"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-compatible =3D "BUCK2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck3: BUCK3 { + regulator-compatible =3D "BUCK3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-compatible =3D "BUCK4"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-compatible =3D "BUCK5"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-compatible =3D "BUCK6"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-compatible =3D "LDO1"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-compatible =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-compatible =3D "LDO3"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-compatible =3D "LDO4"; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-compatible =3D "LDO5"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3600000>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names =3D "default"; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.25.1