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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni X-TBoneOriginalCC: Michel Alex , Waibel Georg , Appelt Andreas , Russell King , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" X-TBoneDomainSigned: false Content-Type: text/plain; charset="utf-8" The SW_RESET definition was incorrectly assigned to bit 14, which is the Digital Restart bit according to the datasheet. This commit corrects SW_RESET to bit 15 and assigns DIG_RESTART to bit 14 as per the datasheet specifications. The SW_RESET define is only used in the phy_reset function, which fully re-initializes the PHY after the reset is performed. The change in the bit definitions should not have any negative impact on the functionality of the PHY. Cc: mailto:stable@vger.kernel.org Signed-off-by: Alex Michel --- drivers/net/phy/dp83822.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index fc247f479257..3ab64e04a01c 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -45,8 +45,8 @@ /* Control Register 2 bits */ #define DP83822_FX_ENABLE BIT(14) =20 -#define DP83822_HW_RESET BIT(15) -#define DP83822_SW_RESET BIT(14) +#define DP83822_SW_RESET BIT(15) +#define DP83822_DIG_RESTART BIT(14) =20 /* PHY STS bits */ #define DP83822_PHYSTS_DUPLEX BIT(2) --=20 2.43.0