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[2001:1c00:3b81:9100:e596:dd7e:500a:9b8c]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b35446f7506sm443091466b.52.2025.09.26.15.46.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Sep 2025 15:46:06 -0700 (PDT) From: Aniruddha Deb Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3776.700.51\)) Subject: [BUG] linux/arch/x86/events/intel/uncore_snbep.c: MCx Channel PCI devices are swapped around Message-Id: Date: Sat, 27 Sep 2025 00:46:03 +0200 Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org To: acme@kernel.org, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org X-Mailer: Apple Mail (2.3776.700.51) Content-Type: text/plain; charset="utf-8" Hi perf subsystem maintainers, The iMC PMC=E2=80=99s in the haswell-EP subsystem have their PCI device ID= =E2=80=99s swapped around. According to page 109 of https://www.intel.com/c= ontent/www/us/en/content-details/671052/intel-xeon-processor-e5-and-e7-v3-f= amily-uncore-performance-monitoring-reference-manual.html, MC0 channel 0 an= d 1 map to 0x2fb4/5 and channel 2/3 map to 0x2fb0/1 respectively. Have atta= ched a small patch illustrating the same. --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3118,32 +3118,32 @@ { /* MC0 Channel 0 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0), }, { /* MC0 Channel 1 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1), }, { /* MC0 Channel 2 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2), }, { /* MC0 Channel 3 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3), }, { /* MC1 Channel 0 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4), }, { /* MC1 Channel 1 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5), }, { /* MC1 Channel 2 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6), }, { /* MC1 Channel 3 */ - PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1), .driver_data =3D UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7), }, I came across this when reading the perf subsystem code to see how offcore = memory controllers are accessed, and where the addresses are defined. Haven= =E2=80=99t had the chance to test it out on hardware yet, so please let me = know if the intel document is wrong and the values entered are correct in p= ractice. Thanks, Aniruddha.