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charset="utf-8" From: Chen Wang Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang Reviewed-by: Guo Ren --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 ++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/ris= cv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 49b4b9c2c101..80cb017974d8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -14,6 +14,18 @@ chosen { }; }; =20 +&cgi_main { + clock-frequency =3D <25000000>; +}; + +&cgi_dpll0 { + clock-frequency =3D <25000000>; +}; + +&cgi_dpll1 { + clock-frequency =3D <25000000>; +}; + &uart0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index 81fda312f988..34c802bd3f9b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -4,8 +4,10 @@ */ =20 /dts-v1/; +#include +#include +#include #include - #include =20 #include "sg2042-cpus.dtsi" @@ -20,12 +22,60 @@ aliases { serial0 =3D &uart0; }; =20 + cgi_main: oscillator0 { + compatible =3D "fixed-clock"; + clock-output-names =3D "cgi_main"; + #clock-cells =3D <0>; + }; + + cgi_dpll0: oscillator1 { + compatible =3D "fixed-clock"; + clock-output-names =3D "cgi_dpll0"; + #clock-cells =3D <0>; + }; + + cgi_dpll1: oscillator2 { + compatible =3D "fixed-clock"; + clock-output-names =3D "cgi_dpll1"; + #clock-cells =3D <0>; + }; + soc: soc { compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; ranges; =20 + pllclk: clock-controller@70300100c0 { + compatible =3D "sophgo,sg2042-pll"; + reg =3D <0x70 0x300100c0 0x0 0x40>; + clocks =3D <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + clock-names =3D "cgi_main", "cgi_dpll0", "cgi_dpll1"; + #clock-cells =3D <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible =3D "sophgo,sg2042-rpgate"; + reg =3D <0x70 0x30010368 0x0 0x98>; + clocks =3D <&clkgen GATE_CLK_RP_CPU_NORMAL>; + clock-names =3D "rpgate"; + #clock-cells =3D <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible =3D "sophgo,sg2042-clkgen"; + reg =3D <0x70 0x30012000 0x0 0x1000>; + clocks =3D <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + clock-names =3D "mpll", + "fpll", + "dpll0", + "dpll1"; + #clock-cells =3D <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; @@ -341,6 +391,9 @@ uart0: serial@7040000000 { interrupt-parent =3D <&intc>; interrupts =3D <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency =3D <500000000>; + clocks =3D <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; resets =3D <&rstgen RST_UART0>; --=20 2.25.1