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Tue, 18 Nov 2025 16:52:31 -0800 From: Nicolin Chen To: , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v6 5/5] PCI: Suspend iommu function prior to resetting a device Date: Tue, 18 Nov 2025 16:52:11 -0800 Message-ID: <9f6caaedc278fe057aacb813d94f44a93d8cab3c.1763512374.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A105:EE_|CYYPR12MB8889:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bb7ffb7-0ba6-46c5-e4fb-08de2705fa49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zlajNCqydDphUuU5Auxtd/Z34pkW92cytRJlVRwp15GawrWZe59tcsjBtMlo?= =?us-ascii?Q?LpghRXLFL6kOXyC0WOGTSBQhxbDOj8QeF0iGqdLdD/PCoAd9rY6V1leFpLuD?= =?us-ascii?Q?T/ggV9j/Idb6L2ZXp84PuB7GkXRV3Y4Rdnou4paiOaloQC9dTP6L79wyTrcH?= =?us-ascii?Q?QOX98RKTdgokESQ5fO3x1KHV71Kp5hGV0LQaXCo6O7RRcyjvQp0QPtMyaaaX?= =?us-ascii?Q?S4CQxrrUDIJrCUNsch6QmA20AV0REe17Y79Lwl2vcbkdbfGvnEYb/3Fez84S?= =?us-ascii?Q?GYdSWvqNRM1r3PkVOw7ALfi9bB3B4ThSt+LLACkCbRa0fdvkboGZOQuT9uqU?= =?us-ascii?Q?3w7hId0ag3B9OnAnFIyuNl5sC50cO1iokdZ7puZPHbvAJSAU2+IOZ1Co9AxM?= =?us-ascii?Q?4FLydOfz4nSX9PSD+wWGOew3YYGiBKgnvPpv5I74b/OsTdvd30LuQ+DjdMbx?= =?us-ascii?Q?+fTeDUTCVHm/jeDz5UkpCstrzNR4YRbJDwQ5BiD863hX5ILSt/jcGi/tMgKs?= =?us-ascii?Q?NI/ibwss3sJZl9pNYxMxhj2q8G7QD4Y0+RKM+5dJcxirUKYNZq79HH8vbDVz?= =?us-ascii?Q?f7jBJw1gxKvLeuiYBpRxQVCTIX6YXKmr7Jm/O0w3gVi08gylUPdeHrtFO0WP?= =?us-ascii?Q?AJ71Y6mybEq+DG0N+gkJOU/zu5KJBct3L2vuZXV8lWd/YMt6LIZkLBH0ozvr?= =?us-ascii?Q?fRBGvxl55jlBYGj2FcKobJ9/TqjNHb0ql5gErEc606R4ubyn5jcs7j74amwe?= =?us-ascii?Q?tTMronXU8qpmfdgEc82GlqqtwFSNx9eWnZNTMkcATCM27h01g9lWCist13oU?= =?us-ascii?Q?6h8TYVWl9NQaOTZG9tMqW3oYwbrIbCkEflrzXFSkg+1gjaSTDC/CW9ukL4o8?= =?us-ascii?Q?BXUdeNi7FA+bUtSLpsBxCvQmoeWFSQBCZVGF2DEGqAT8YhTbV8ztyfkw/ON+?= =?us-ascii?Q?6F9qcepxHuwpg8cYlZu0QyYclOs00t2uRYx8+0GO1VaYZnbM0MqrlJG4Qy7S?= =?us-ascii?Q?53Dt0tWgxo+3uZg/m/PHOCrFx9jle+Vih077GHVTY2XlPbQFi92vApS/ObQX?= =?us-ascii?Q?mkZGv4YplthVKjwUEx6Eh+nOEu/dFBOArdqWM6LDLh173t9NYVGcRtRjfj2F?= =?us-ascii?Q?FXHPkC9ozpKtspEJVG3uPiaZ16jvcuSrot75kjjFCMYXBggnxOrVnAeWS+eH?= =?us-ascii?Q?PtTJVwViAcpAE6pquqWPvHw7hDn1/P2cSFZ3MnwOZxiVEIfIsAFOfe/59357?= =?us-ascii?Q?bKNcKBg2X5TWjSx3sPRQc+lR40bDqdk4xcNQxlMBD9GpNbomtylVutwYEIzn?= =?us-ascii?Q?tSzaw5WXLA8+Dk6Bf7wt24u7/pLu96VSqyC5+m5ikirAxHOzkIVQRi5gV0fI?= =?us-ascii?Q?bTZ6ZU31ykAN83nFJ0bT3ja8Eov+c0F725FnfSfGnMbgPH2WgLlEwMcIdrkX?= =?us-ascii?Q?QZPus6PlbMd7roDdZ6APASTR/HUyc3LhqvnAtuug80/XRFM69ZF8FOHpm40d?= =?us-ascii?Q?fLFjLOnnGcD8ii1UgIk2WIStKBdiQL9rMuwmdF4cT06tLj1TnBbEiu7+CoLC?= =?us-ascii?Q?MJrGb/qUMNGGy5Yzbq0=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2025 00:52:55.8673 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bb7ffb7-0ba6-46c5-e4fb-08de2705fa49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A105.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8889 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe r6.0, sec 10.3.1 IMPLEMENTATION NOTE recommends SW to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. The IOMMU subsystem provides pci_dev_reset_iommu_prepare/done() callback helpers for this matter. Use them in all the existing reset functions. This will attach the device to its iommu_group->blocking_domain during the device reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats(), if necessary - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/pci/pci-acpi.c | 13 +++++++-- drivers/pci/pci.c | 65 +++++++++++++++++++++++++++++++++++++----- drivers/pci/quirks.c | 19 +++++++++++- 3 files changed, 87 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..651d9b5561fff 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -971,6 +972,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle =3D ACPI_HANDLE(&dev->dev); + int ret; =20 if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -978,12 +980,19 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool prob= e) if (probe) return 0; =20 + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret =3D -ENOTTY; } =20 - return 0; + pci_dev_reset_iommu_done(dev); + return ret; } =20 bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006cc..da0cf0f041516 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -4478,13 +4480,22 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4493,7 +4504,10 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); =20 - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_dev_reset_iommu_done(dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); =20 @@ -4521,6 +4535,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); =20 static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret; int pos; u8 cap; =20 @@ -4547,10 +4562,17 @@ static int pci_af_flr(struct pci_dev *dev, bool pro= be) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF f= unction level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4560,7 +4582,10 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) */ msleep(100); =20 - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_dev_reset_iommu_done(dev); + return ret; } =20 /** @@ -4581,6 +4606,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4595,6 +4621,12 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (dev->current_state !=3D PCI_D0) return -EINVAL; =20 + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + csr &=3D ~PCI_PM_CTRL_STATE_MASK; csr |=3D PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4605,7 +4637,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); =20 - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + pci_dev_reset_iommu_done(dev); + return ret; } =20 /** @@ -5033,10 +5067,20 @@ static int pci_reset_bus_function(struct pci_dev *d= ev, bool probe) return -ENOTTY; } =20 + rc =3D pci_dev_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc); + return rc; + } + rc =3D pci_dev_reset_slot_function(dev, probe); if (rc !=3D -ENOTTY) - return rc; - return pci_parent_bus_reset(dev, probe); + goto done; + + rc =3D pci_parent_bus_reset(dev, probe); +done: + pci_dev_reset_iommu_done(dev); + return rc; } =20 static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) @@ -5060,6 +5104,12 @@ static int cxl_reset_bus_function(struct pci_dev *de= v, bool probe) if (rc) return -ENOTTY; =20 + rc =3D pci_dev_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc); + return rc; + } + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val =3D reg; } else { @@ -5074,6 +5124,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev= , bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); =20 + pci_dev_reset_iommu_done(dev); return rc; } =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 214ed060ca1b3..75b6786af01b8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -21,6 +21,7 @@ #include #include /* isa_dma_bridge_buggy */ #include +#include #include #include #include @@ -4226,6 +4227,22 @@ static const struct pci_dev_reset_methods pci_dev_re= set_methods[] =3D { { 0 } }; =20 +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + ret =3D i->reset(dev, probe); + pci_dev_reset_iommu_done(dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4240,7 +4257,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool = probe) i->vendor =3D=3D (u16)PCI_ANY_ID) && (i->device =3D=3D dev->device || i->device =3D=3D (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } =20 return -ENOTTY; --=20 2.43.0