From nobody Sat Nov 30 10:38:45 2024 Received: from mail03.siengine.com (mail03.siengine.com [43.240.192.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98C23174EDB; Tue, 10 Sep 2024 06:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=43.240.192.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725948841; cv=none; b=olngmGJWmDfNXP4vyb9g88mMz5U2h66m1qvff9JarMvzCNf4FC++VNOKGbIEApwCF9o5ms3Msk7r6HOQBeafPtqbMJq9F2Bgh19A+1X3Krb2iLw2/Bx8cl++rzT+ZHO8FcdTLj68/QEj/szWNZmRLkmOulyu1w4VHJqYsKk6QvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725948841; c=relaxed/simple; bh=VVyuSYwcQjPqDmfwABc0FqZX2TZU9Scqu5CiLmwmd8g=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=DZ4J44JBBhL8gaRmK5y7ArRyX8FEOq0+99ZkdQkZI2jlSeze6lf/YYNOFiciXsTaLiTuT9FUr6mQRqZlBTUqAzwZBazMu6sp2dkzrqpw1Q7yJrQ6/0S9BFuHnFcahi/icWbEjkqKLGQxtV+FAxKjiMYoAVKyAH95YnhvEVasuFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=siengine.com; spf=pass smtp.mailfrom=siengine.com; arc=none smtp.client-ip=43.240.192.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=siengine.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=siengine.com Received: from dsgsiengine01.siengine.com ([10.8.1.61]) by mail03.siengine.com with ESMTPS id 48A6DD1q027077 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 10 Sep 2024 14:13:13 +0800 (+08) (envelope-from hongchi.peng@siengine.com) Received: from SEEXMB03-2019.siengine.com (SEEXMB03-2019.siengine.com [10.8.1.33]) by dsgsiengine01.siengine.com (SkyGuard) with ESMTPS id 4X2tfw0RHnz7ZMhG; Tue, 10 Sep 2024 14:13:12 +0800 (CST) Received: from SEEXMB05-2019.siengine.com (10.8.1.153) by SEEXMB03-2019.siengine.com (10.8.1.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1544.11; Tue, 10 Sep 2024 14:13:11 +0800 Received: from SEEXMB03-2019.siengine.com (10.8.1.33) by SEEXMB05-2019.siengine.com (10.8.1.153) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1544.9; Tue, 10 Sep 2024 14:13:11 +0800 Received: from localhost (10.12.10.38) by SEEXMB03-2019.siengine.com (10.8.1.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA) id 15.2.1544.11 via Frontend Transport; Tue, 10 Sep 2024 14:13:11 +0800 From: Kimriver Liu To: CC: , , , , , , Subject: [PATCH v8] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled Date: Tue, 10 Sep 2024 14:13:09 +0800 Message-ID: <9d181a45f3edf92364c9e6b729638f0b3f2e7baa.1725946886.git.kimriver.liu@siengine.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: [10.8.1.61]; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: mail03.siengine.com 48A6DD1q027077 Content-Type: text/plain; charset="utf-8" It was observed issuing ABORT bit(IC_ENABLE[1]) will not work when IC_ENABLE is already disabled. Check if ENABLE bit(IC_ENABLE[0]) is disabled when the master is holding SCL low. If ENABLE bit is disabled, the software need enable it before trying to issue ABORT bit. otherwise, the controller ignores any write to ABORT bit. Signed-off-by: Kimriver Liu Reviewed-by: Mika Westerberg Acked-by: Jarkko Nikula --- V7->V8: 1.calculate this delay based on the actual speed in use fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)) 2. add Reviewed-by: Mika Westerberg V6->V7: 1. add Subject versioning [PATCH v7] 2. change fsleep(25) to usleep_range(25, 250) 3. Add macro definition DW_iC_ENABLE_ENABLE to fix compile errors | Reported-by: kernel test robot | Closes:https://lore.kernel.org/oe-kbuild-all/202409082011.9JF6aYsk-lkp= @intel.com/ 4. base: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/= commit/?h=3Dmaster V5->V6: restore i2c_dw_is_master_idling() function checking V4->V5: delete master idling checking V3->V4: 1. update commit messages and add patch version and changelog 2. move print the error message in i2c_dw_xfer V2->V3: change (!enable) to (!(enable & DW_IC_ENABLE_ENABLE)) V1->V2: used standard words in function names and addressed review comments link to V1: https://lore.kernel.org/lkml/20240904064224.2394-1-kimriver.liu@siengine.co= m/ --- drivers/i2c/busses/i2c-designware-common.c | 13 +++++++++++++ drivers/i2c/busses/i2c-designware-core.h | 1 + drivers/i2c/busses/i2c-designware-master.c | 22 ++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index e8a688d04aee..3ff50ec942e9 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -441,6 +441,7 @@ int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) =20 void __i2c_dw_disable(struct dw_i2c_dev *dev) { + struct i2c_timings *t =3D &dev->timings; unsigned int raw_intr_stats; unsigned int enable; int timeout =3D 100; @@ -453,6 +454,18 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev) =20 abort_needed =3D raw_intr_stats & DW_IC_INTR_MST_ON_HOLD; if (abort_needed) { + if (!(enable & DW_IC_ENABLE_ENABLE)) { + regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); + enable |=3D DW_IC_ENABLE_ENABLE; + /* + * Wait 10 times the signaling period of the highest I2C + * transfer supported by the driver (for 400KHz this is + * 25us) to ensure the I2C ENABLE bit is already set + * as described in the DesignWare I2C databook. + */ + fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); + } + regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); ret =3D regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, !(enable & DW_IC_ENABLE_ABORT), 10, diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index e9606c00b8d1..e45daedad967 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -109,6 +109,7 @@ DW_IC_INTR_RX_UNDER | \ DW_IC_INTR_RD_REQ) =20 +#define DW_IC_ENABLE_ENABLE BIT(0) #define DW_IC_ENABLE_ABORT BIT(1) =20 #define DW_IC_STATUS_ACTIVITY BIT(0) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index c7e56002809a..132b7237c004 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -253,6 +253,19 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) __i2c_dw_write_intr_mask(dev, DW_IC_INTR_MASTER_MASK); } =20 +static bool i2c_dw_is_master_idling(struct dw_i2c_dev *dev) +{ + u32 status; + + regmap_read(dev->map, DW_IC_STATUS, &status); + if (!(status & DW_IC_STATUS_MASTER_ACTIVITY)) + return true; + + return !regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, + !(status & DW_IC_STATUS_MASTER_ACTIVITY), + 1100, 20000); +} + static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev) { u32 val; @@ -788,6 +801,15 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg m= sgs[], int num) goto done; } =20 + /* + * This happens rarely and is hard to reproduce. Debug trace + * showed that IC_STATUS had value of 0x23 when STOP_DET occurred, + * if disable IC_ENABLE.ENABLE immediately that can result in + * IC_RAW_INTR_STAT.MASTER_ON_HOLD holding SCL low. + */ + if (!i2c_dw_is_master_idling(dev)) + dev_err(dev->dev, "I2C master not idling\n"); + /* * We must disable the adapter before returning and signaling the end * of the current transfer. Otherwise the hardware might continue --=20 2.17.1