From nobody Sat Nov 30 16:37:54 2024 Received: from mail03.siengine.com (mail03.siengine.com [43.240.192.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46E281AD416 for ; Mon, 9 Sep 2024 06:52:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=43.240.192.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725864723; cv=none; b=ucLBMiW+qFQ8l7QKpjbyci9f6z0APGa+i1YhE+2vZeSQ2yHRfyDTdatlXCu+wG5oysNePDTrcnUGjJbQhDZznBipzmVmMOSUgsa4WinSgH+AEDPK5gcJ0RYxR2/CIUbnDH8QKdtdjASftr5V+MG8QgAq5SnAxMtuirjEE7e6U6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725864723; c=relaxed/simple; bh=6esrUczR8oysIyzNBKCBPAjvleuW+wajfkwDu72CqIw=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=PkUlzMCKhoFtO2NTi99qt50ZH2aJm/nMASfuhsVHahXyTZkFe7xLPAOCEq4scYMxN+NELK9jN2cxNMwc3RViKlSMyMrM+lWyyhaENYAOx+/OkEebCgeEgFV/lrIblf0VX1XMB2YdQD4SD+YcRi+OeU8UQbDpIis3mDuka47aWCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=siengine.com; spf=pass smtp.mailfrom=siengine.com; arc=none smtp.client-ip=43.240.192.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=siengine.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=siengine.com Received: from dsgsiengine01.siengine.com ([10.8.1.61]) by mail03.siengine.com with ESMTPS id 4896okHL032940 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 9 Sep 2024 14:50:46 +0800 (+08) (envelope-from kimriver.liu@siengine.com) Received: from SEEXMB03-2019.siengine.com (SEEXMB03-2019.siengine.com [10.8.1.33]) by dsgsiengine01.siengine.com (SkyGuard) with ESMTPS id 4X2HXj626Rz7ZMkV; Mon, 9 Sep 2024 14:50:45 +0800 (CST) Received: from SEEXMB03-2019.siengine.com (10.8.1.33) by SEEXMB03-2019.siengine.com (10.8.1.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1544.11; Mon, 9 Sep 2024 14:50:45 +0800 Received: from SEEXMB03-2019.siengine.com ([fe80::23e0:1bbb:3ec9:73fe]) by SEEXMB03-2019.siengine.com ([fe80::23e0:1bbb:3ec9:73fe%16]) with mapi id 15.02.1544.011; Mon, 9 Sep 2024 14:50:45 +0800 From: =?gb2312?B?TGl1IEtpbXJpdmVyL8H1vfC60w==?= To: kernel test robot , "jarkko.nikula@linux.intel.com" CC: "oe-kbuild-all@lists.linux.dev" , "andriy.shevchenko@linux.intel.com" , "mika.westerberg@linux.intel.com" , "jsd@semihalf.com" , "andi.shyti@kernel.org" , "linux-i2c@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled Thread-Topic: [PATCH] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled Thread-Index: AQHa/2duFR8zehOY/kSHdEPBwRT+f7JNYfWAgAGYwOA= Date: Mon, 9 Sep 2024 06:50:45 +0000 Message-ID: <9bbcf9e663ea4a12a44fd46afd800e16@siengine.com> References: <20240905074211.2278-1-kimriver.liu@siengine.com> <202409082011.9JF6aYsk-lkp@intel.com> In-Reply-To: <202409082011.9JF6aYsk-lkp@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DKIM-Results: [10.8.1.61]; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: mail03.siengine.com 4896okHL032940 Content-Type: text/plain; charset="utf-8" Hi jarkko=20 -----Original Message----- From: kernel test robot =20 Sent: 2024=E5=B9=B49=E6=9C=888=E6=97=A5 21:32 To: Liu Kimriver/=E5=88=98=E9=87=91=E6=B2=B3 ; j= arkko.nikula@linux.intel.com Cc: oe-kbuild-all@lists.linux.dev; andriy.shevchenko@linux.intel.com; mika.= westerberg@linux.intel.com; jsd@semihalf.com; andi.shyti@kernel.org; linux-= i2c@vger.kernel.org; linux-kernel@vger.kernel.org; Liu Kimriver/=E5=88=98= =E9=87=91=E6=B2=B3 Subject: Re: [PATCH] i2c: designware: fix master is holding SCL low while E= NABLE bit is disabled >>Hi kimriver, >>kernel test robot noticed the following build errors: >> [auto build test ERROR on andi-shyti/i2c/i2c-host] >> [also build test ERROR on linus/master v6.11-rc6 next-20240906] >> [If your patch is applied to the wrong git tree, kindly drop us a note. >>And when submitting patch, we suggest to use '--base' as documented in >>https://git-scm.com/docs/git-format-patch#_base_tree_information] I applied patch to the wrong git tree last week , I had resent V7 patch To= resolve build test ERROR. patch Subject: [PATCH v7] i2c: designware: fix master is holding SCL low w= hile ENABLE bit is disabled New patch link:=20 https://lore.kernel.org/all/20240909015646.2285-1-kimriver.liu@siengine.c= om/ The patch rebase on the latest Linux v6.11.0-rc6 (89f5e14d05b) branch (the = latest linux master branch) >>url: https://github.com/intel-lab-lkp/linux/commits/kimriver-liu/i2c-d= esignware-fix-master-is-holding-SCL-low-while-ENABLE-bit-is-disabled/202409= 05-154711 >>base: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.= git i2c/i2c-host >>patch link: https://lore.kernel.org/r/20240905074211.2278-1-kimriver.l= iu%40siengine.com >>patch subject: [PATCH] i2c: designware: fix master is holding SCL low whi= le ENABLE bit is disabled >>config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20240908= /202409082011.9JF6aYsk-lkp@intel.com/config) >>compiler: sh4-linux-gcc (GCC) 14.1.0 >>reproduce (this is a W=3D1 build): (https://download.01.org/0day-ci/archi= ve/20240908/202409082011.9JF6aYsk-lkp@intel.com/reproduce) >>If you fix the issue in a separate patch/commit (i.e. not just a new vers= ion of >>the same patch/commit), kindly add following tags >>| Reported-by: kernel test robot >>| Closes: https://lore.kernel.org/oe-kbuild-all/202409082011.9JF6aYsk-lkp= @intel.com/ >>All errors (new ones prefixed by >>): >> drivers/i2c/busses/i2c-designware-common.c: In function '__i2c_dw_disa= ble': >>>> drivers/i2c/busses/i2c-designware-common.c:538:32: error: 'DW_IC_ENABL= E_ENABLE' undeclared (first use in this function); did you mean 'DW_IC_ENAB= LE_STATUS'? >> 538 | if (!(enable & DW_IC_ENABLE_ENABLE)) { >> | ^~~~~~~~~~~~~~~~~~~ >> | DW_IC_ENABLE_STATUS >> drivers/i2c/busses/i2c-designware-common.c:538:32: note: each undeclar= ed identifier is reported only once for each function it appears in I fixexd the issue at the same commit as In V7 version patch link: =20 https://lore.kernel.org/all/20240909015646.2285-1-kimriver.liu@siengine.= com/=20 patch Subject: [PATCH v7] i2c: designware: fix master is holding SCL low wh= ile ENABLE bit is disabled Declaration DW_IC_ENABLE_ENABLE as follow: =20 diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index e9606c00b8d1..e45daedad967 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -109,6 +109,7 @@ DW_IC_INTR_RX_UNDER | \ DW_IC_INTR_RD_REQ) =20 +#define DW_IC_ENABLE_ENABLE BIT(0) #define DW_IC_ENABLE_ABORT BIT(1) =20 #define DW_IC_STATUS_ACTIVITY BIT(0) >>vim +538 drivers/i2c/busses/i2c-designware-common.c >> 523=09 >> 524 void __i2c_dw_disable(struct dw_i2c_dev *dev) >> 525 { >> 526 unsigned int raw_intr_stats; >> 527 unsigned int enable; >> 528 int timeout =3D 100; >> 529 bool abort_needed; >> 530 unsigned int status; >> 531 int ret; >> 532=09 >> 533 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); >> 534 regmap_read(dev->map, DW_IC_ENABLE, &enable); >> 535=09 >> 536 abort_needed =3D raw_intr_stats & DW_IC_INTR_MST_ON_HOLD; >> 537 if (abort_needed) { >> > 538 if (!(enable & DW_IC_ENABLE_ENABLE)) { >> 539 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); >> 540 enable |=3D DW_IC_ENABLE_ENABLE; >> 541=09 >> 542 /* >> 543 * Wait two ic_clk delay when enabling the i2c to ensure ENABLE= bit >> 544 * is already set by the driver (for 400KHz this is 25us) >> 545 * as described in the DesignWare I2C databook. >> 546 */ >> 547 fsleep(25); >> 548 } >> 549=09 >> 550 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT= ); >> 551 ret =3D regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, >> 552 !(enable & DW_IC_ENABLE_ABORT), 10, >> 553 100); >> 554 if (ret) >> 555 dev_err(dev->dev, "timeout while trying to abort current transf= er\n"); >> 556 } >> 557=09 >> 558 do { >> 559 __i2c_dw_disable_nowait(dev); >> 560 /* >> 561 * The enable status register may be unimplemented, but >> 562 * in that case this test reads zero and exits the loop. >> 563 */ >> 564 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); >> 565 if ((status & 1) =3D=3D 0) >> 566 return; >> 567=09 >> 568 /* >> 569 * Wait 10 times the signaling period of the highest I2C >> 570 * transfer supported by the driver (for 400KHz this is >> 571 * 25us) as described in the DesignWare I2C databook. >> 572 */ >> 573 usleep_range(25, 250); >> 574 } while (timeout--); >> 575=09 >> 576 dev_warn(dev->dev, "timeout in disabling adapter\n"); >> 577 } >> 578=09 ------------------------------------------ Best Regards Kimriver Liu