From nobody Fri Oct 3 20:25:47 2025 Received: from FR4P281CU032.outbound.protection.outlook.com (mail-germanywestcentralazon11022126.outbound.protection.outlook.com [40.107.149.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEDB834DCC1; Tue, 26 Aug 2025 14:42:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.149.126 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756219324; cv=fail; b=YEClr01/eZ907YHsgCztEzwbXmuufdMKX+PeJlwsG1aKeNAhOWJeBhq0nGB34Va2h31PBQ8foUhuURe4pIdkbLcAJz2u0Sziom+xBQOil5YoSa1EJct2uPjvtZgKBtLc4HXfrsEYmj46j/D7wUlfZaRGFMNC6/C3WRjjklDWJO8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756219324; c=relaxed/simple; bh=3NoUCNlpKbvqvM40sShPEFeQ+FSt4UsnNVhNA2l5jmI=; h=From:To:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=sSIHiJNL32kEl8RYolFr3auzTRCCAGPbEQAojB9l9+h5bAWfSdovWBzbY/sjpEB2nGt7NKE73K6Sfhwz/MpwcOC4jckMYWfUQOL9aefEGqLrZL8FI39QugmzCyU11P+3s+udbdFHNZsHJ2w0qpa3UbJWrgko6FtxOhEHc6n94Qg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=adtran.com; spf=pass smtp.mailfrom=adtran.com; dkim=pass (1024-bit key) header.d=adtran.com header.i=@adtran.com header.b=Q6KfWxE2; arc=fail smtp.client-ip=40.107.149.126 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=adtran.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=adtran.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=adtran.com header.i=@adtran.com header.b="Q6KfWxE2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PofHm1GEhxRY9kAQq/A/y0U3lGr5K0MaMTrnUjsEnuQMVOsk0PnlM6cXbi5+kO8GuIz9DudcR/NGs+P3FslWipMZGKX+qp1grgxyQoogNTb+pN5KgI6dN/YZeIagK5OClg8nqxefQiOIktoT7AqRomr/fV7rET+45mE1iBVtjq9HJGstqUHvTlJ/ufAxcnfbv1FzLsg9+dEaZE1EsXIKM3ovt5DyuSS0JtDcqgsxOMQjczinMrUDZlzGkmanXnynHTmdT8b5bo6SCG5A0IRarJo7yMItM12Vocr0sWPGR6sQpEaGh7PXfksE5gK+bkRKX4a3mq8C3HKiLHH3M7rQGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3NoUCNlpKbvqvM40sShPEFeQ+FSt4UsnNVhNA2l5jmI=; b=bF3ZH3hxhiXjrkQnZAPPTCoEFMciwCeWuiXg6N2TPk0hOSqiBH/gWL3KO7uT3FKDHc2cHCYw8AewP31txM0bUZgUgAAsrZ6Si3soGC+ZFRGcdRe4bkVvAtY28a3yhpeewPY+cd7WTnZA3EOnRburvCui+2VAUBGEAramAemlqy6jKgG5xI6Outwu9f2Bs5GynI3ZwozbpsGQ5tbMmno0rrWirBdiGQ9q8Zkt5e360GPSLM4E6ZrpJemYj3R2DY0ccFTLe/ks41uttPpDJ8M/QN88EM12Ae9hrIiYjqo0e9pTTowZalvpAxIs64R2nQIjdu208ekyBO71B1z/IxK74Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=adtran.com; dmarc=pass action=none header.from=adtran.com; dkim=pass header.d=adtran.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adtran.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3NoUCNlpKbvqvM40sShPEFeQ+FSt4UsnNVhNA2l5jmI=; b=Q6KfWxE2CwSRVpgOrfjS27PMK1tCNZ1EsyIk+NArTwr5azJHXzn4PvtA4CpYMz/bUd0BVR3YTPdoVeD3+3Zn8Za3letzuau4QrFTwJ0lzKnr9Q/gP4zO3ERT4yayKYr6b+1NQ4ZV2ix/WliUylc3MUg7H6relYTdEkxkzFQ2AIA= Received: from FR3PPF3200C8D6F.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d18:2::126) by FR3P281MB2219.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:32::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.22; Tue, 26 Aug 2025 14:41:58 +0000 Received: from FR3PPF3200C8D6F.DEUP281.PROD.OUTLOOK.COM ([fe80::92f0:48d2:2be9:13c6]) by FR3PPF3200C8D6F.DEUP281.PROD.OUTLOOK.COM ([fe80::92f0:48d2:2be9:13c6%6]) with mapi id 15.20.9052.019; Tue, 26 Aug 2025 14:41:58 +0000 From: Piotr Kubik To: Oleksij Rempel , Kory Maincent , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH net-next v7 2/2] net: pse-pd: Add Si3474 PSE controller driver Thread-Topic: [PATCH net-next v7 2/2] net: pse-pd: Add Si3474 PSE controller driver Thread-Index: AQHcFpeTHMVMVXMin0qtd6wXP56VEA== Date: Tue, 26 Aug 2025 14:41:58 +0000 Message-ID: <9b72c8cd-c8d3-4053-9c80-671b9481d166@adtran.com> References: <6af537dc-8a52-4710-8a18-dcfbb911cf23@adtran.com> In-Reply-To: <6af537dc-8a52-4710-8a18-dcfbb911cf23@adtran.com> Accept-Language: pl-PL, en-US Content-Language: pl-PL X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=adtran.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: FR3PPF3200C8D6F:EE_|FR3P281MB2219:EE_ x-ms-office365-filtering-correlation-id: 75835a50-1a3f-44cf-7b20-08dde4aeb5c0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|366016|7416014|376014|1800799024|38070700018|921020; x-microsoft-antispam-message-info: =?utf-8?B?VjZBekIrVnN5Q0Q1NEZXbXpOZ3JWOXYwT3d0aFRDRmFhTkJ2aUM1S2JUUzF6?= =?utf-8?B?MHF1czk5N0F3Wjdxd0FZN1BuLzVIZjJ4STF2MG1najJDK2NRbDNoZGJSVjRW?= =?utf-8?B?L290YW80Y0MwNm5YK2s2Z08zalY0cDBFRzRSU3ZXQUFiZ1M2SCtIang1c3pk?= =?utf-8?B?bUlYdGpGeUhYdnA2UVJCckRKR0RnVVFjVy8yVXNtK2xqcFRMV056WFU0cFh1?= =?utf-8?B?cTJpb1V4UTV6MGZ0QzFvZU9jaERIQlN2dnN6bWpiNG9vd3pVYjVnRHBFMWV3?= =?utf-8?B?SVFBMkhtRFpqaEtONHkyZDQveW5YamQreVZ0cjNGV2JmM2VyS1Vlb0V2Z3BO?= =?utf-8?B?L0RDUXBSUHFNMTR0QzI5V004Q04rcnFmMXg2VUVaVTJkdzdoY1ZDKzZBYlF4?= =?utf-8?B?KysxUmpiemNLR2kwQ3cxZkt5eE5NRGFSNUp6a1ArN3YxZ0Z5c2FoWE55RGg2?= =?utf-8?B?Umk2QnRmN1NTUjlEcVFLcUFBc2g5S29vQldTQTBuUzBBaEVwcDFkMXlObnYz?= =?utf-8?B?ZSsrREN2dkZpUUw4Zi8yYmxaZ0xQa1dGemdkNFJoM1RCK0dSZmRmZkFQUXJT?= =?utf-8?B?NmJNK25WT2I3WHhtUlhOTUtQeUs4MDVPOG51NzBrOTE2RHNyR0F1MldIQmVD?= =?utf-8?B?L3oxTmVNUnpFSUxvQlRGZUozbERDdlZoZGRGSk5COGRUdVVpOGR1aEdIWG1i?= =?utf-8?B?Ky9XaWR5WXNXS1dybk1GbFo0V2VXQ1JZdlJYRkJrTkV2WDBFZWowUjkwK2tO?= =?utf-8?B?SzlvL3YwbjJBREo5WHp0VE5VV21pK21JUnFqSC9ucWdtN0Z2VmdDM2xBUHdv?= =?utf-8?B?Q2hxcmFqa0MxdEhwcVE0U0tLTTNRc0wwWHR0U3BNSndReDk1RXpMTG9SU2JT?= =?utf-8?B?V2J6MjV1ZUc3NlB0TWg5Lzd1ZGJzb1p0Zk11VEZOckQzVmdoc0tLaG9rKzFa?= =?utf-8?B?ajIyWlBJeEVLR0VmR0EzSUp6bllEcWpEM2xzVGFQSElzSDJIUEROcHVCREN1?= =?utf-8?B?Y2ppNTlJUm51L0JqVVdwV0plcTRPemVQS091RjFrcFhLbjU0MERrclAvRkkx?= =?utf-8?B?em5KcHgrZkFVL0o3SnhiQkN6b2QrMWMxaHlIamhOOFVxZjNXanhZMDB1Kzcy?= =?utf-8?B?dnBjeml1eC9HaFBURnFlaTRFaC9TODlWWmtCTTRqZnJIQkZhUUdvNTZ0SDFl?= =?utf-8?B?RjlrZEJJdnJlVmVVYS9VVE8wd1E2RTR5TU54ZUpjeno4UWpXdEZwTXBTKzVR?= =?utf-8?B?NWpnTTd3Z0dZSUkvcVFJZ0I3NFdKeHBEYU1qTGZSWXBtazJLNXJZeFB6bXBG?= =?utf-8?B?Z01hbU9LV3JzVVFQK1Nvdm5HWk8yRXo4OGRpUm4wS3JYbXVXV2crVHNJR3VB?= =?utf-8?B?R08wb0RDVlplS2hFNlhIeXlPZ2dzYnFwM2tNaTVFVTFOckhWeFN3QjZydG15?= =?utf-8?B?TXNJRTRXeWdWMXZGMDc1WEs2NmhFRFIwTjRSMmFVYWthc0VwdnpZQUMxVTE2?= =?utf-8?B?aVVWbXpwYjUrUVdoOEhhRkhweTY5SmVRajRUKytXcnhhUTdyTGdBUDlBZlhs?= =?utf-8?B?c25kQlU3QlZaZWxGVVc1dlFTb09ZY2hLa2RlS3FRTlVucUhIdFd6WDNqQU5X?= =?utf-8?B?Z2VJNlIzUExHUU9TT1VISXNFd1lkeG14MDEyaThLWE51OWNaNVNvMHVFaXVO?= =?utf-8?B?TzROdUtVOUdGWmxjcXE1ZGNVdG1GeGhqeEQ4YUZnay9kWWthL2FWUVRBUGxh?= =?utf-8?B?WG1nckQ5TzVRaGpDUEJyVzVuZHJ1bU1MQVhUK1dob1NuY1Zna1U2U3FqUXJU?= =?utf-8?B?NkNZSUFyZ3NzbHppYlVNdDQ5YXdldmwvWjNvdGExcjJaekY4Rnl0Y3ZVRnVs?= =?utf-8?B?N2lnbFltTHE1L0JZckEvMXEwMlJxT2U5Yk4wVnNDR0E2WlZsU0JZalVHR0p5?= =?utf-8?B?WEhaVFZuMXJaM0JuRUJud0pOOHFSQ0EzWXFpckx3aDdtNHcyUW5YQUY2ZXA0?= =?utf-8?Q?9q2SYXT0BQvessKTxoTDkFTjUBOn34=3D?= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:FR3PPF3200C8D6F.DEUP281.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(366016)(7416014)(376014)(1800799024)(38070700018)(921020);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?aFkwWHUyYnlKeXBFNXZzbkx0UnplKytlU2paT0Flb0VKL2lqVDcvZEl0Y3Bz?= =?utf-8?B?QUZQYlVUeDQ3ZFJKMDQzdy90ZHg4VHdqUWo3WVFNdktqS2YyMEFhRWMvdWFQ?= =?utf-8?B?UkVtZlFPT1JyYXBuVDFwQ1Q0WXdCaHFhYU1zd3M2YnBNeTFkNWRLdUEyYXAx?= =?utf-8?B?VkJBeFN2S2gyWklTSUs2K2wyRVpxL3k1Q2kyWHpjVlZtdFZCRTNnanl4YVlq?= =?utf-8?B?MnMyZjZ6V0JQMUJ2QndOS2c4SGQzaysxYlhpajY4ZnZ1YW9XNHRxK2duVVcy?= =?utf-8?B?eXhTMTFJTHBIR1ZpdUtGZUNUVGhDNS9sOEoyNnp1Rk9OTS9ROUhBaDR5aHBR?= =?utf-8?B?NFJlN0JaeGhkUEJ1RS9FbVJPWkFLcW1DZWQ2aXBNNVlQNmloMGVEU2hLKzRX?= =?utf-8?B?bkNaUTY4OXlLbkhvNHBYNE14REhGUDFqSy9Odm00cWlPMHY4dWtaMW8wbFFl?= =?utf-8?B?QnVwZ1RSbjVDQjN5d2lFNnRab2IwMGY1NWx1K0VNRUZ3THNQL0orUUw1M3Ux?= =?utf-8?B?MGs4dkRmRDdFcEx3ODlUaUJsVGMvbVpwOXcvTDkvbHFNdXc1WUsrWDVWMWFa?= =?utf-8?B?SkZmdkpBM3JnWGhOVnI2dTNhM3FrNUswT3JwNWV5dFJtQ0kvaDdVMlFSM0RM?= =?utf-8?B?aFZwREh5SktWSVk4ckNsSUlxRlM3MXA3RnhLZG1jcFpuaU5sTW40VFNkKzJi?= =?utf-8?B?SFQzb2pNNkFWd29nR1VlaGV2aUhONm1RaXI2bSs3eXlseit5VURmMkJGKzVV?= =?utf-8?B?eHdmZndwVjErYXluTHVlcmY4QThIaHdjc1ltTVA1Ly80M3dUR2Z4TmFMQ2lu?= =?utf-8?B?cm0zbGhNL280WXNnS2hWMno4c3U2UnduYU5VTTk3ZGg2c1ZHVjE4M1RVM3Uz?= =?utf-8?B?NmROeUU1ZkFQSXlzUGNDeCszNTJtZ0x2T1RKekdFOWx0Q3Q5ZitBSGpUdHR5?= =?utf-8?B?VVluZnlsYjN6TnhFVHQ2emxad3R1OGxVZzF1RXVVYkEzaFB6NGl1LzlXU3Zh?= =?utf-8?B?bWJtNlF6aytCRXJGNE8wUmtOMjBPdXp4TTVjaGFzMERJQzBHZW0wQlVvcTk3?= =?utf-8?B?VjJtM0ZvODl4RUw2UVc4Tmh0ZXZaUXl6bHVrZGtSSkVXRnhMTWFVUS9CVjE5?= =?utf-8?B?UEZBTE9vdm84bDZaNE1NM0ticUpoZkpkdlhhNmNWQ2kvbDcrdUk2akJxMXY1?= =?utf-8?B?azQrWGw1ZW1WQTZFcTlraHZyZE80VS9uSjczR3FXQnNvUnZwVHR0ZGNFSlZL?= =?utf-8?B?b3BXUlh1cUZQeTN3Z0xsR3hiUEJDaTZTNTBka1cwZkxMeEEwOS9IYWI0K3hi?= =?utf-8?B?b21FR3BRS1JHc3BoMmRIVHBXaDNCcU5ZTGRmblBNU3hLNCtabEptMHcwak1U?= =?utf-8?B?MStzZ0pIODh5ZXNKTFZoMkdraE43OXZYL0VobFBQR3hRdXR3NXhPOXhNLzhI?= =?utf-8?B?SjNQb3hxUG5oTGNpSDdRMXdUeWNua21iK01qWVRZTFpZMmhJRUVBWDNyeTd5?= =?utf-8?B?d3dHdys4WXFKTnNQUkw2YXFlNEJwekxrUVByclpQYVRsc292cmdFcWVGUVNo?= =?utf-8?B?ZmM3R09waElXbDRJTk9kOTF3VUJSanBQZW4xZlVXUkZRLzY2TVIxeSt0T3ho?= =?utf-8?B?Rm1ZeW1pTUJ4RWJ3ZTViK1ozbklvcldhaE1xak1ENEtXOXQ0em5iODFBand4?= =?utf-8?B?Q1IvWDBlc1BHL1BGODE1ckFHUTZmYmNaOEVSZ2FRREFYb1dUekNNbmo2NEVo?= =?utf-8?B?YVVVZndFbWlFNGRTU0l2b3hvQTF4c1RXeXh2dnAvRE1ZN2svZUVxa3NhemV1?= =?utf-8?B?N0U5UTJzWGZ0ZnpJczZCM1luc1FHVVZCQ1lCOGVZYWEzUHFkZitXeExSNG1z?= =?utf-8?B?MGVGSitVOEEzRlJ2ekdhanVBcCtIekNQQ1hxdXFHbmtMRjA4VHdpMEZDWUZx?= =?utf-8?B?TTNpZjNtbmhOcDZRQ3d6KzRzU3hqUU12b2l5bytjcjhUSEozbEhDRzFaTlpy?= =?utf-8?B?YkE0VGNUYnlRVDJGWkQ3cUxiS2t1N1Ywdm1KZEp3Y1VpL1dKYUkwL2JvTmNF?= =?utf-8?B?SW9BMjFqZkR4cUdUWE5GMkRXVEUyMWJRLy9STUczN2xSSFZaVVphdVR0M0sr?= =?utf-8?Q?zzHyj1MeJ2gPgJZbdTaPqo+UG?= Content-Type: text/plain; charset="utf-8" Content-ID: Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: adtran.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: FR3PPF3200C8D6F.DEUP281.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 75835a50-1a3f-44cf-7b20-08dde4aeb5c0 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2025 14:41:58.0671 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 423946e4-28c0-4deb-904c-a4a4b174fb3f X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dDnIzZUjTdk2anaA9EdF4/zWLATMnDwITrdLWdyUWs7QSBhIhoLgXvaD86DSaszUOWGt90dvm8d9aQKkuMI6NA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: FR3P281MB2219 From: Piotr Kubik Add a driver for the Skyworks Si3474 I2C Power Sourcing Equipment controller. Driver supports basic features of Si3474 IC: - get port status, - get port power, - get port voltage, - enable/disable port power. Only 4p configurations are supported at this moment. Signed-off-by: Piotr Kubik Reviewed-by: Kory Maincent --- Changes in v7: - Add return with error if DTS is missing second PI pair configuration (4= p only). Changes in v6: - Remove unnecessary chan id range checks. - Fix return value for incorrect DT channels parse. - Simplify bit logic for 'is_enabled' assignment. - Remove unnecessary init values assignment. - Fix code style issues (apply correct reverse xmas tree notation, remove= extra brackets). Changes in v5: - Remove inline function declarations. - Fix code style issues (apply reverse xmas tree notation, remove extra b= rackets). - Remove unnecessary "!=3D 0" check. Changes in v4: - Remove parsing of pse-pis node; now relies solely on the pcdev->pi[x] p= rovided by the framework. - Set the DETECT_CLASS_ENABLE register, ensuring reliable PI power-up wit= hout artificial delays. - Introduce helper macros for bit manipulation logic. - Add si3474_get_channels() and si3474_get_chan_client() helpers to reduc= e redundant code. - Kconfig: Clarify that only 4-pair PSE configurations are supported. - Fix second channel voltage read if the first one is inactive. - Avoid reading currents and computing power when PI voltage is zero. Changes in v3: - Use _scoped version of for_each_child_of_node(). - Remove redundant return value assignments in si3474_get_of_channels(). - Change dev_info() to dev_dbg() on successful probe. - Rename all instances of "slave" to "secondary". - Register devm cleanup action for ancillary i2c, simplifying cleanup log= ic in si3474_i2c_probe(). - Add explicit return 0 on successful probe. - Drop unnecessary .remove callback. Changes in v2: - Handle both IC quads via single driver instance - Add architecture & terminology description comment - Change pi_enable, pi_disable, pi_get_admin_state to use PORT_MODE regis= ter - Rename power ports to 'pi' - Use i2c_smbus_write_byte_data() for single byte registers - Coding style improvements --- drivers/net/pse-pd/Kconfig | 11 + drivers/net/pse-pd/Makefile | 1 + drivers/net/pse-pd/si3474.c | 578 ++++++++++++++++++++++++++++++++++++ 3 files changed, 590 insertions(+) create mode 100644 drivers/net/pse-pd/si3474.c diff --git a/drivers/net/pse-pd/Kconfig b/drivers/net/pse-pd/Kconfig index 7fab916a7f46..7ef29657ee5d 100644 --- a/drivers/net/pse-pd/Kconfig +++ b/drivers/net/pse-pd/Kconfig @@ -32,6 +32,17 @@ config PSE_PD692X0 To compile this driver as a module, choose M here: the module will be called pd692x0. =20 +config PSE_SI3474 + tristate "Si3474 PSE controller" + depends on I2C + help + This module provides support for Si3474 regulator based Ethernet + Power Sourcing Equipment. + Only 4-pair PSE configurations are supported. + + To compile this driver as a module, choose M here: the + module will be called si3474. + config PSE_TPS23881 tristate "TPS23881 PSE controller" depends on I2C diff --git a/drivers/net/pse-pd/Makefile b/drivers/net/pse-pd/Makefile index 9d2898b36737..cc78f7ea7f5f 100644 --- a/drivers/net/pse-pd/Makefile +++ b/drivers/net/pse-pd/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PSE_CONTROLLER) +=3D pse_core.o =20 obj-$(CONFIG_PSE_REGULATOR) +=3D pse_regulator.o obj-$(CONFIG_PSE_PD692X0) +=3D pd692x0.o +obj-$(CONFIG_PSE_SI3474) +=3D si3474.o obj-$(CONFIG_PSE_TPS23881) +=3D tps23881.o diff --git a/drivers/net/pse-pd/si3474.c b/drivers/net/pse-pd/si3474.c new file mode 100644 index 000000000000..aa07ffbce54d --- /dev/null +++ b/drivers/net/pse-pd/si3474.c @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the Skyworks Si3474 PoE PSE Controller + * + * Chip Architecture & Terminology: + * + * The Si3474 is a single-chip PoE PSE controller managing 8 physical power + * delivery channels. Internally, it's structured into two logical "Quads". + * + * Quad 0: Manages physical channels ('ports' in datasheet) 0, 1, 2, 3 + * Quad 1: Manages physical channels ('ports' in datasheet) 4, 5, 6, 7 + * + * Each Quad is accessed via a separate I2C address. The base address rang= e is + * set by hardware pins A1-A4, and the specific address selects Quad 0 (us= ually + * the lower/even address) or Quad 1 (usually the higher/odd address). + * See datasheet Table 2.2 for the address mapping. + * + * While the Quads manage channel-specific operations, the Si3474 package = has + * several resources shared across the entire chip: + * - Single RESETb input pin. + * - Single INTb output pin (signals interrupts from *either* Quad). + * - Single OSS input pin (Emergency Shutdown). + * - Global I2C Address (0x7F) used for firmware updates. + * - Global status monitoring (Temperature, VDD/VPWR Undervoltage Lockout). + * + * Driver Architecture: + * + * To handle the mix of per-Quad access and shared resources correctly, th= is + * driver treats the entire Si3474 package as one logical device. The driv= er + * instance associated with the primary I2C address (Quad 0) takes ownersh= ip. + * It discovers and manages the I2C client for the secondary address (Quad= 1). + * This primary instance handles shared resources like IRQ management and + * registers a single PSE controller device representing all logical PIs. + * Internal functions route I2C commands to the appropriate Quad's i2c_cli= ent + * based on the target channel or PI. + * + * Terminology Mapping: + * + * - "PI" (Power Interface): Refers to the logical PSE port as defined by + * IEEE 802.3 (typically corresponds to an RJ45 connector). This is the + * `id` (0-7) used in the pse_controller_ops. + * - "Channel": Refers to one of the 8 physical power control paths within + * the Si3474 chip itself (hardware channels 0-7). This terminology is + * used internally within the driver to avoid confusion with 'ports'. + * - "Quad": One of the two internal 4-channel management units within the + * Si3474, each accessed via its own I2C address. + * + * Relationship: + * - A 2-Pair PoE PI uses 1 Channel. + * - A 4-Pair PoE PI uses 2 Channels. + * + * ASCII Schematic: + * + * +-----------------------------------------------------+ + * | Si3474 Chip | + * | | + * | +---------------------+ +---------------------+ | + * | | Quad 0 | | Quad 1 | | + * | | Channels 0, 1, 2, 3 | | Channels 4, 5, 6, 7 | | + * | +----------^----------+ +-------^-------------+ | + * | I2C Addr 0 | | I2C Addr 1 | + * | +------------------------+ | + * | (Primary Driver Instance) (Managed by Primary) | + * | | + * | Shared Resources (affect whole chip): | + * | - Single INTb Output -> Handled by Primary | + * | - Single RESETb Input | + * | - Single OSS Input -> Handled by Primary | + * | - Global I2C Addr (0x7F) for Firmware Update | + * | - Global Status (Temp, VDD/VPWR UVLO) | + * +-----------------------------------------------------+ + * | | | | | | | | + * Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 (Physical Channels) + * + * Example Mapping (Logical PI to Physical Channel(s)): + * * 2-Pair Mode (8 PIs): + * PI 0 -> Ch 0 + * PI 1 -> Ch 1 + * ... + * PI 7 -> Ch 7 + * * 4-Pair Mode (4 PIs): + * PI 0 -> Ch 0 + Ch 1 (Managed via Quad 0 Addr) + * PI 1 -> Ch 2 + Ch 3 (Managed via Quad 0 Addr) + * PI 2 -> Ch 4 + Ch 5 (Managed via Quad 1 Addr) + * PI 3 -> Ch 6 + Ch 7 (Managed via Quad 1 Addr) + * (Note: Actual mapping depends on Device Tree and PORT_REMAP config) + */ + +#include +#include +#include +#include +#include + +#define SI3474_MAX_CHANS 8 + +#define MANUFACTURER_ID 0x08 +#define IC_ID 0x05 +#define SI3474_DEVICE_ID (MANUFACTURER_ID << 3 | IC_ID) + +/* Misc registers */ +#define VENDOR_IC_ID_REG 0x1B +#define TEMPERATURE_REG 0x2C +#define FIRMWARE_REVISION_REG 0x41 +#define CHIP_REVISION_REG 0x43 + +/* Main status registers */ +#define POWER_STATUS_REG 0x10 +#define PORT_MODE_REG 0x12 +#define DETECT_CLASS_ENABLE_REG 0x14 + +/* PORTn Current */ +#define PORT1_CURRENT_LSB_REG 0x30 + +/* PORTn Current [mA], return in [nA] */ +/* 1000 * ((PORTn_CURRENT_MSB << 8) + PORTn_CURRENT_LSB) / 16384 */ +#define SI3474_NA_STEP (1000 * 1000 * 1000 / 16384) + +/* VPWR Voltage */ +#define VPWR_LSB_REG 0x2E +#define VPWR_MSB_REG 0x2F + +/* PORTn Voltage */ +#define PORT1_VOLTAGE_LSB_REG 0x32 + +/* VPWR Voltage [V], return in [uV] */ +/* 60 * (( VPWR_MSB << 8) + VPWR_LSB) / 16384 */ +#define SI3474_UV_STEP (1000 * 1000 * 60 / 16384) + +/* Helper macros */ +#define CHAN_IDX(chan) ((chan) % 4) +#define CHAN_BIT(chan) BIT(CHAN_IDX(chan)) +#define CHAN_UPPER_BIT(chan) BIT(CHAN_IDX(chan) + 4) + +#define CHAN_MASK(chan) (0x03U << (2 * CHAN_IDX(chan))) +#define CHAN_REG(base, chan) ((base) + (CHAN_IDX(chan) * 4)) + +struct si3474_pi_desc { + u8 chan[2]; + bool is_4p; +}; + +struct si3474_priv { + struct i2c_client *client[2]; + struct pse_controller_dev pcdev; + struct device_node *np; + struct si3474_pi_desc pi[SI3474_MAX_CHANS]; +}; + +static struct si3474_priv *to_si3474_priv(struct pse_controller_dev *pcdev) +{ + return container_of(pcdev, struct si3474_priv, pcdev); +} + +static void si3474_get_channels(struct si3474_priv *priv, int id, + u8 *chan0, u8 *chan1) +{ + *chan0 =3D priv->pi[id].chan[0]; + *chan1 =3D priv->pi[id].chan[1]; +} + +static struct i2c_client *si3474_get_chan_client(struct si3474_priv *priv, + u8 chan) +{ + return (chan < 4) ? priv->client[0] : priv->client[1]; +} + +static int si3474_pi_get_admin_state(struct pse_controller_dev *pcdev, int= id, + struct pse_admin_state *admin_state) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + bool is_enabled; + u8 chan0, chan1; + s32 ret; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) { + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN; + return ret; + } + + is_enabled =3D ret & (CHAN_MASK(chan0) | CHAN_MASK(chan1)); + + if (is_enabled) + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; + else + admin_state->c33_admin_state =3D + ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; + + return 0; +} + +static int si3474_pi_get_pw_status(struct pse_controller_dev *pcdev, int i= d, + struct pse_pw_status *pw_status) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + bool delivering; + u8 chan0, chan1; + s32 ret; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + ret =3D i2c_smbus_read_byte_data(client, POWER_STATUS_REG); + if (ret < 0) { + pw_status->c33_pw_status =3D ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN; + return ret; + } + + delivering =3D ret & (CHAN_UPPER_BIT(chan0) | CHAN_UPPER_BIT(chan1)); + + if (delivering) + pw_status->c33_pw_status =3D + ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; + else + pw_status->c33_pw_status =3D ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; + + return 0; +} + +static int si3474_get_of_channels(struct si3474_priv *priv) +{ + struct pse_pi *pi; + u32 chan_id; + u8 pi_no; + s32 ret; + + for (pi_no =3D 0; pi_no < SI3474_MAX_CHANS; pi_no++) { + pi =3D &priv->pcdev.pi[pi_no]; + bool pairset_found =3D false; + u8 pairset_no; + + for (pairset_no =3D 0; pairset_no < 2; pairset_no++) { + if (!pi->pairset[pairset_no].np) + continue; + + pairset_found =3D true; + + ret =3D of_property_read_u32(pi->pairset[pairset_no].np, + "reg", &chan_id); + if (ret) { + dev_err(&priv->client[0]->dev, + "Failed to read channel reg property\n"); + return ret; + } + if (chan_id > SI3474_MAX_CHANS) { + dev_err(&priv->client[0]->dev, + "Incorrect channel number: %d\n", chan_id); + return -EINVAL; + } + + priv->pi[pi_no].chan[pairset_no] =3D chan_id; + /* Mark as 4-pair if second pairset is present */ + priv->pi[pi_no].is_4p =3D (pairset_no =3D=3D 1); + } + + if (pairset_found && !priv->pi[pi_no].is_4p) { + dev_err(&priv->client[0]->dev, + "Second pairset is missing for PI %pOF, only 4p configs are supported\= n", + pi->np); + return -EINVAL; + } + } + + return 0; +} + +static int si3474_setup_pi_matrix(struct pse_controller_dev *pcdev) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + s32 ret; + + ret =3D si3474_get_of_channels(priv); + if (ret < 0) + dev_warn(&priv->client[0]->dev, + "Unable to parse DT PSE power interface matrix\n"); + + return ret; +} + +static int si3474_pi_enable(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + u8 chan0, chan1; + s32 ret; + u8 val; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Release PI from shutdown */ + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) + return ret; + + val =3D (u8)ret; + val |=3D CHAN_MASK(chan0); + val |=3D CHAN_MASK(chan1); + + ret =3D i2c_smbus_write_byte_data(client, PORT_MODE_REG, val); + if (ret) + return ret; + + /* DETECT_CLASS_ENABLE must be set when using AUTO mode, + * otherwise PI does not power up - datasheet section 2.10.2 + */ + val =3D CHAN_BIT(chan0) | CHAN_UPPER_BIT(chan0) | + CHAN_BIT(chan1) | CHAN_UPPER_BIT(chan1); + + ret =3D i2c_smbus_write_byte_data(client, DETECT_CLASS_ENABLE_REG, val); + if (ret) + return ret; + + return 0; +} + +static int si3474_pi_disable(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + u8 chan0, chan1; + s32 ret; + u8 val; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Set PI in shutdown mode */ + ret =3D i2c_smbus_read_byte_data(client, PORT_MODE_REG); + if (ret < 0) + return ret; + + val =3D (u8)ret; + val &=3D ~CHAN_MASK(chan0); + val &=3D ~CHAN_MASK(chan1); + + ret =3D i2c_smbus_write_byte_data(client, PORT_MODE_REG, val); + if (ret) + return ret; + + return 0; +} + +static int si3474_pi_get_chan_current(struct si3474_priv *priv, u8 chan) +{ + struct i2c_client *client; + u64 tmp_64; + s32 ret; + u8 reg; + + client =3D si3474_get_chan_client(priv, chan); + + /* Registers 0x30 to 0x3d */ + reg =3D CHAN_REG(PORT1_CURRENT_LSB_REG, chan); + + ret =3D i2c_smbus_read_word_data(client, reg); + if (ret < 0) + return ret; + + tmp_64 =3D ret * SI3474_NA_STEP; + + /* uA =3D nA / 1000 */ + tmp_64 =3D DIV_ROUND_CLOSEST_ULL(tmp_64, 1000); + return (int)tmp_64; +} + +static int si3474_pi_get_chan_voltage(struct si3474_priv *priv, u8 chan) +{ + struct i2c_client *client; + s32 ret; + u32 val; + u8 reg; + + client =3D si3474_get_chan_client(priv, chan); + + /* Registers 0x32 to 0x3f */ + reg =3D CHAN_REG(PORT1_VOLTAGE_LSB_REG, chan); + + ret =3D i2c_smbus_read_word_data(client, reg); + if (ret < 0) + return ret; + + val =3D ret * SI3474_UV_STEP; + + return (int)val; +} + +static int si3474_pi_get_voltage(struct pse_controller_dev *pcdev, int id) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + struct i2c_client *client; + u8 chan0, chan1; + s32 ret; + + si3474_get_channels(priv, id, &chan0, &chan1); + client =3D si3474_get_chan_client(priv, chan0); + + /* Check which channels are enabled*/ + ret =3D i2c_smbus_read_byte_data(client, POWER_STATUS_REG); + if (ret < 0) + return ret; + + /* Take voltage from the first enabled channel */ + if (ret & CHAN_BIT(chan0)) + ret =3D si3474_pi_get_chan_voltage(priv, chan0); + else if (ret & CHAN_BIT(chan1)) + ret =3D si3474_pi_get_chan_voltage(priv, chan1); + else + /* 'should' be no voltage in this case */ + return 0; + + return ret; +} + +static int si3474_pi_get_actual_pw(struct pse_controller_dev *pcdev, int i= d) +{ + struct si3474_priv *priv =3D to_si3474_priv(pcdev); + u8 chan0, chan1; + u32 uV, uA; + u64 tmp_64; + s32 ret; + + ret =3D si3474_pi_get_voltage(&priv->pcdev, id); + + /* Do not read currents if voltage is 0 */ + if (ret <=3D 0) + return ret; + uV =3D ret; + + si3474_get_channels(priv, id, &chan0, &chan1); + + ret =3D si3474_pi_get_chan_current(priv, chan0); + if (ret < 0) + return ret; + uA =3D ret; + + ret =3D si3474_pi_get_chan_current(priv, chan1); + if (ret < 0) + return ret; + uA +=3D ret; + + tmp_64 =3D uV; + tmp_64 *=3D uA; + /* mW =3D uV * uA / 1000000000 */ + return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); +} + +static const struct pse_controller_ops si3474_ops =3D { + .setup_pi_matrix =3D si3474_setup_pi_matrix, + .pi_enable =3D si3474_pi_enable, + .pi_disable =3D si3474_pi_disable, + .pi_get_actual_pw =3D si3474_pi_get_actual_pw, + .pi_get_voltage =3D si3474_pi_get_voltage, + .pi_get_admin_state =3D si3474_pi_get_admin_state, + .pi_get_pw_status =3D si3474_pi_get_pw_status, +}; + +static void si3474_ancillary_i2c_remove(void *data) +{ + struct i2c_client *client =3D data; + + i2c_unregister_device(client); +} + +static int si3474_i2c_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct si3474_priv *priv; + u8 fw_version; + s32 ret; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_err(dev, "i2c check functionality failed\n"); + return -ENXIO; + } + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret =3D i2c_smbus_read_byte_data(client, VENDOR_IC_ID_REG); + if (ret < 0) + return ret; + + if (ret !=3D SI3474_DEVICE_ID) { + dev_err(dev, "Wrong device ID: 0x%x\n", ret); + return -ENXIO; + } + + ret =3D i2c_smbus_read_byte_data(client, FIRMWARE_REVISION_REG); + if (ret < 0) + return ret; + fw_version =3D ret; + + ret =3D i2c_smbus_read_byte_data(client, CHIP_REVISION_REG); + if (ret < 0) + return ret; + + dev_dbg(dev, "Chip revision: 0x%x, firmware version: 0x%x\n", + ret, fw_version); + + priv->client[0] =3D client; + i2c_set_clientdata(client, priv); + + priv->client[1] =3D i2c_new_ancillary_device(priv->client[0], "secondary", + priv->client[0]->addr + 1); + if (IS_ERR(priv->client[1])) + return PTR_ERR(priv->client[1]); + + ret =3D devm_add_action_or_reset(dev, si3474_ancillary_i2c_remove, priv->= client[1]); + if (ret < 0) { + dev_err(&priv->client[1]->dev, "Cannot register remove callback\n"); + return ret; + } + + ret =3D i2c_smbus_read_byte_data(priv->client[1], VENDOR_IC_ID_REG); + if (ret < 0) { + dev_err(&priv->client[1]->dev, "Cannot access secondary PSE controller\n= "); + return ret; + } + + if (ret !=3D SI3474_DEVICE_ID) { + dev_err(&priv->client[1]->dev, + "Wrong device ID for secondary PSE controller: 0x%x\n", ret); + return -ENXIO; + } + + priv->np =3D dev->of_node; + priv->pcdev.owner =3D THIS_MODULE; + priv->pcdev.ops =3D &si3474_ops; + priv->pcdev.dev =3D dev; + priv->pcdev.types =3D ETHTOOL_PSE_C33; + priv->pcdev.nr_lines =3D SI3474_MAX_CHANS; + + ret =3D devm_pse_controller_register(dev, &priv->pcdev); + if (ret) { + dev_err(dev, "Failed to register PSE controller: 0x%x\n", ret); + return ret; + } + + return 0; +} + +static const struct i2c_device_id si3474_id[] =3D { + { "si3474" }, + {} +}; +MODULE_DEVICE_TABLE(i2c, si3474_id); + +static const struct of_device_id si3474_of_match[] =3D { + { + .compatible =3D "skyworks,si3474", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, si3474_of_match); + +static struct i2c_driver si3474_driver =3D { + .probe =3D si3474_i2c_probe, + .id_table =3D si3474_id, + .driver =3D { + .name =3D "si3474", + .of_match_table =3D si3474_of_match, + }, +}; +module_i2c_driver(si3474_driver); + +MODULE_AUTHOR("Piotr Kubik "); +MODULE_DESCRIPTION("Skyworks Si3474 PoE PSE Controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0