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[72.189.67.6]) by smtp.gmail.com with ESMTPSA id h7-20020a0561220b6700b0047dbd48bc44sm238059vkf.17.2023.07.20.11.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 11:49:59 -0700 (PDT) From: William Breathitt Gray To: Bartosz Golaszewski , Linus Walleij Cc: Lars-Peter Clausen , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, William Breathitt Gray Subject: [RESEND PATCH 1/2] gpio: 104-dio-48e: Add Counter/Timer support Date: Thu, 20 Jul 2023 14:49:43 -0400 Message-ID: <9b159da19bb78df21c1dc24161188c9b8452720a.1689878150.git.william.gray@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 104-DIO-48E features an 8254 Counter/Timer chip providing three counter/timers which can be used for frequency measurement, frequency output, pulse width modulation, pulse width measurement, event count, etc. The counter/timers use the same addresses as PPI 0 (addresses 0x0 to 0x3), so a raw_spinlock_t is used to synchronize operations between the two regmap mappings to prevent clobbering. Reviewed-by: Linus Walleij Signed-off-by: William Breathitt Gray --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-104-dio-48e.c | 127 ++++++++++++++++++++++++++++---- 2 files changed, 112 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e382dfebad7c..49466a148678 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -858,6 +858,7 @@ config GPIO_104_DIO_48E select REGMAP_IRQ select GPIOLIB_IRQCHIP select GPIO_I8255 + select I8254 help Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E, 104-DIO-24E). The base port addresses for the devices may be diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48= e.c index 8ff5f4ff5958..4df9becaf349 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include =20 #include "gpio-i8255.h" @@ -37,6 +39,8 @@ MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line n= umbers"); =20 #define DIO48E_ENABLE_INTERRUPT 0xB #define DIO48E_DISABLE_INTERRUPT DIO48E_ENABLE_INTERRUPT +#define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD +#define DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING DIO48E_ENABLE_COUNTER_TIME= R_ADDRESSING #define DIO48E_CLEAR_INTERRUPT 0xF =20 #define DIO48E_NUM_PPI 2 @@ -75,18 +79,20 @@ static const struct regmap_access_table dio48e_precious= _table =3D { .yes_ranges =3D dio48e_precious_ranges, .n_yes_ranges =3D ARRAY_SIZE(dio48e_precious_ranges), }; -static const struct regmap_config dio48e_regmap_config =3D { - .reg_bits =3D 8, - .reg_stride =3D 1, - .val_bits =3D 8, - .io_port =3D true, - .max_register =3D 0xF, - .wr_table =3D &dio48e_wr_table, - .rd_table =3D &dio48e_rd_table, - .volatile_table =3D &dio48e_volatile_table, - .precious_table =3D &dio48e_precious_table, - .cache_type =3D REGCACHE_FLAT, - .use_raw_spinlock =3D true, + +static const struct regmap_range pit_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x3), +}; +static const struct regmap_range pit_rd_ranges[] =3D { + regmap_reg_range(0x0, 0x2), +}; +static const struct regmap_access_table pit_wr_table =3D { + .yes_ranges =3D pit_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_wr_ranges), +}; +static const struct regmap_access_table pit_rd_table =3D { + .yes_ranges =3D pit_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_rd_ranges), }; =20 /* only bit 3 on each respective Port C supports interrupts */ @@ -102,14 +108,56 @@ static const struct regmap_irq dio48e_regmap_irqs[] = =3D { =20 /** * struct dio48e_gpio - GPIO device private data structure + * @lock: synchronization lock to prevent I/O race conditions * @map: Regmap for the device + * @regs: virtual mapping for device registers + * @flags: IRQ flags saved during locking * @irq_mask: Current IRQ mask state on the device */ struct dio48e_gpio { + raw_spinlock_t lock; struct regmap *map; + void __iomem *regs; + unsigned long flags; unsigned int irq_mask; }; =20 +static void dio48e_regmap_lock(void *lock_arg) __acquires(&dio48egpio->loc= k) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + unsigned long flags; + + raw_spin_lock_irqsave(&dio48egpio->lock, flags); + dio48egpio->flags =3D flags; +} + +static void dio48e_regmap_unlock(void *lock_arg) __releases(&dio48egpio->l= ock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + + raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags); +} + +static void pit_regmap_lock(void *lock_arg) __acquires(&dio48egpio->lock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + unsigned long flags; + + raw_spin_lock_irqsave(&dio48egpio->lock, flags); + dio48egpio->flags =3D flags; + + iowrite8(0x00, dio48egpio->regs + DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING); +} + +static void pit_regmap_unlock(void *lock_arg) __releases(&dio48egpio->lock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + + ioread8(dio48egpio->regs + DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING); + + raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags); +} + static int dio48e_handle_mask_sync(const int index, const unsigned int mask_buf_def, const unsigned int mask_buf, @@ -176,6 +224,9 @@ static int dio48e_probe(struct device *dev, unsigned in= t id) struct i8255_regmap_config config =3D {}; void __iomem *regs; struct regmap *map; + struct regmap_config dio48e_regmap_config; + struct regmap_config pit_regmap_config; + struct i8254_regmap_config pit_config; int err; struct regmap_irq_chip *chip; struct dio48e_gpio *dio48egpio; @@ -187,21 +238,58 @@ static int dio48e_probe(struct device *dev, unsigned = int id) return -EBUSY; } =20 + dio48egpio =3D devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); + if (!dio48egpio) + return -ENOMEM; + regs =3D devm_ioport_map(dev, base[id], DIO48E_EXTENT); if (!regs) return -ENOMEM; =20 + dio48egpio->regs =3D regs; + + raw_spin_lock_init(&dio48egpio->lock); + + dio48e_regmap_config =3D (struct regmap_config) { + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .lock =3D dio48e_regmap_lock, + .unlock =3D dio48e_regmap_unlock, + .lock_arg =3D dio48egpio, + .io_port =3D true, + .wr_table =3D &dio48e_wr_table, + .rd_table =3D &dio48e_rd_table, + .volatile_table =3D &dio48e_volatile_table, + .precious_table =3D &dio48e_precious_table, + .cache_type =3D REGCACHE_FLAT, + }; + map =3D devm_regmap_init_mmio(dev, regs, &dio48e_regmap_config); if (IS_ERR(map)) return dev_err_probe(dev, PTR_ERR(map), "Unable to initialize register map\n"); =20 - dio48egpio =3D devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); - if (!dio48egpio) - return -ENOMEM; - dio48egpio->map =3D map; =20 + pit_regmap_config =3D (struct regmap_config) { + .name =3D "i8254", + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .lock =3D pit_regmap_lock, + .unlock =3D pit_regmap_unlock, + .lock_arg =3D dio48egpio, + .io_port =3D true, + .wr_table =3D &pit_wr_table, + .rd_table =3D &pit_rd_table, + }; + + pit_config.map =3D devm_regmap_init_mmio(dev, regs, &pit_regmap_config); + if (IS_ERR(pit_config.map)) + return dev_err_probe(dev, PTR_ERR(pit_config.map), + "Unable to initialize i8254 register map\n"); + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; @@ -225,6 +313,12 @@ static int dio48e_probe(struct device *dev, unsigned i= nt id) if (err) return dev_err_probe(dev, err, "IRQ registration failed\n"); =20 + pit_config.parent =3D dev; + + err =3D devm_i8254_regmap_register(dev, &pit_config); + if (err) + return err; + config.parent =3D dev; config.map =3D map; config.num_ppi =3D DIO48E_NUM_PPI; @@ -245,3 +339,4 @@ module_isa_driver_with_irq(dio48e_driver, num_dio48e, n= um_irq); MODULE_AUTHOR("William Breathitt Gray "); MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(I8254); --=20 2.41.0