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charset="utf-8" Add device tree documentation for AD4134 24-Bit, 4-channel simultaneous sampling, precision ADC. Reviewed-by: Conor Dooley Signed-off-by: Marcelo Schmitt --- Change log v3 -> v4: - Renamed clock option "xtal1-xtal2" to "xtal" (making it similar to other = bindings). - Use oneOf for ldoin-supply choice. - Dropped properties set to their defaults from the example. I believe the changes were not disruptive so I kept Conor's review tag. .../bindings/iio/adc/adi,ad4134.yaml | 191 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4134.ya= ml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4134.yaml new file mode 100644 index 000000000000..ea6d7e026419 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4134 ADC + +maintainers: + - Marcelo Schmitt + +description: | + The AD4134 is a quad channel, low noise, simultaneous sampling, precision + analog-to-digital converter (ADC). + Specifications can be found at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4134.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4134 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + avdd5-supply: + description: A 5V supply that powers the chip's analog circuitry. + + dvdd5-supply: + description: A 5V supply that powers the chip's digital circuitry. + + iovdd-supply: + description: + A 1.8V supply that sets the logic levels for the digital interface p= ins. + + refin-supply: + description: + A 4.096V or 5V supply that serves as reference for ADC conversions. + + avdd1v8-supply: + description: A 1.8V supply used by the analog circuitry. + + dvdd1v8-supply: + description: A 1.8V supply used by the digital circuitry. + + clkvdd-supply: + description: A 1.8V supply for the chip's clock management circuit. + + ldoin-supply: + description: + A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and = CLKVDD + pins. + + clocks: + maxItems: 1 + description: + Required external clock source. Can specify either a crystal or CMOS= clock + source. If an external crystal is set, connect the CLKSEL pin to IOV= DD. + Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clo= ck + signal to the XTAL2/CLKIN pin. + + clock-names: + enum: + - xtal + - clkin + default: clkin + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + regulators: + type: object + description: + list of regulators provided by this controller. + + properties: + vcm-output: + $ref: /schemas/regulator/regulator.yaml# + type: object + unevaluatedProperties: false + + additionalProperties: false + + reset-gpios: + maxItems: 1 + + powerdown-gpios: + description: + Active low GPIO connected to the /PDN pin. Forces the device into fu= ll + power-down mode when brought low. Pull this input to IOVDD for normal + operation. + maxItems: 1 + + odr-gpios: + description: + GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mo= de. + maxItems: 1 + + adi,asrc-mode: + $ref: /schemas/types.yaml#/definitions/string + description: + Asynchronous Sample Rate Converter (ASRC) operation mode control inp= ut. + Describes whether the MODE pin is set to a high level (for master mo= de + operation) or to a low level (for slave mode operation). + enum: [ high, low ] + default: low + + adi,dclkio: + description: + DCLK pin I/O direction control for when the device operates in Pin C= ontrol + Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is a= t a + high level (which configures DCLK as an output) or to set to a low l= evel + (configuring DCLK for input). + enum: [ out, in ] + default: in + + adi,dclkmode: + description: + DCLK mode control for when the device operates in Pin Control Slave = Mode + or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is s= et to + a high level (configuring the DCLK to operate in free running mode) = or + to a low level (to configure DCLK to operate in gated mode). + enum: [ free-running, gated ] + default: gated + +required: + - compatible + - reg + - avdd5-supply + - dvdd5-supply + - iovdd-supply + - refin-supply + - clocks + - clock-names + +oneOf: + - required: + - ldoin-supply + - required: + - avdd1v8-supply + - dvdd1v8-supply + - clkvdd-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4134"; + reg =3D <0>; + + spi-max-frequency =3D <1000000>; + + reset-gpios =3D <&gpio0 86 GPIO_ACTIVE_LOW>; + odr-gpios =3D <&gpio0 87 GPIO_ACTIVE_HIGH>; + powerdown-gpios =3D <&gpio0 88 GPIO_ACTIVE_LOW>; + + clocks =3D <&sys_clk>; + clock-names =3D "clkin"; + + avdd5-supply =3D <&avdd5>; + dvdd5-supply =3D <&dvdd5>; + iovdd-supply =3D <&iovdd>; + refin-supply =3D <&refin>; + avdd1v8-supply =3D <&avdd1v8>; + dvdd1v8-supply =3D <&dvdd1v8>; + clkvdd-supply =3D <&clkvdd>; + + regulators { + vcm_reg: vcm-output { + regulator-name =3D "ad4134-vcm"; + }; + }; + + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 2e8825b8ccef..3f9f6dd96ae4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1458,6 +1458,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml F: drivers/iio/adc/ad4130.c =20 +ANALOG DEVICES INC AD4134 DRIVER +M: Marcelo Schmitt +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml + ANALOG DEVICES INC AD4170-4 DRIVER M: Marcelo Schmitt L: linux-iio@vger.kernel.org --=20 2.51.0