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Fri, 13 Jun 2025 08:05:37 -0700 (PDT) Received: from geday ([2804:7f2:800b:838f::dead:c001]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2365deb04a6sm15372025ad.178.2025.06.13.08.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 08:05:36 -0700 (PDT) Date: Fri, 13 Jun 2025 12:05:31 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH v4 1/5] PCI: rockchip: Use standard PCIe defines Message-ID: <992ab6278af59b8f2f82521bf4611f69a916bbe1.1749827015.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current code uses custom-defined register offsets and bitfields for standard PCIe registers. Change to using standard PCIe defines. Suggested-By: Bjorn Helgaas Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 44 ++++++++++----------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index b9e7a8710cf0..65653218b9ab 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -40,18 +40,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip= _pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockch= ip) @@ -269,7 +269,7 @@ static void rockchip_pcie_set_power_limit(struct rockch= ip_pcie *rockchip) scale =3D 3; /* 0.001x */ curr =3D curr / 1000; /* convert to mA */ power =3D (curr * 3300) / 1000; /* milliwatt */ - while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { + while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) { if (!scale) { dev_warn(rockchip->dev, "invalid power supply\n"); return; @@ -278,10 +278,10 @@ static void rockchip_pcie_set_power_limit(struct rock= chip_pcie *rockchip) power =3D power / 10; } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); - status |=3D (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | - (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCA= P); + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); } =20 /** @@ -309,14 +309,14 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) rockchip_pcie_set_power_limit(rockchip); =20 /* Set RC's clock architecture as common clock */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D PCI_EXP_LNKSTA_SLC << 16; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); =20 /* Set RC's RCB to 128 */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D PCI_EXP_LNKCTL_RCB; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); =20 /* Enable Gen1 training */ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, @@ -341,9 +341,9 @@ static int rockchip_pcie_host_init_port(struct rockchip= _pcie *rockchip) * Enable retrain for gen2. This should be configured only after * gen1 finished. */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); status |=3D PCI_EXP_LNKCTL_RL; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); =20 err =3D readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, status, PCIE_LINK_IS_GEN2(status), 20, @@ -380,15 +380,15 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) =20 /* Clear L0s from RC's link cap */ if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); - status &=3D ~PCIE_RC_CONFIG_LINK_CAP_L0S; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= AP); + status &=3D ~PCI_EXP_LNKCAP_ASPM_L0S; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP= ); } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); - status &=3D ~PCIE_RC_CONFIG_DCSR_MPS_MASK; - status |=3D PCIE_RC_CONFIG_DCSR_MPS_256; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCT= L); + status &=3D ~PCI_EXP_DEVCTL_PAYLOAD; + status |=3D PCI_EXP_DEVCTL_PAYLOAD_256B; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); =20 return 0; err_power_off_phy: --=20 2.49.0