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Sun, 4 Feb 2024 06:59:52 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id HpxjGOg1v2WKZwAAD6G6ig (envelope-from ); Sun, 04 Feb 2024 06:59:52 +0000 From: Andrea della Porta To: Vinod Koul , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , dmaengine@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Maxime Ripard , Dom Cobley , Phil Elwell , Andrea della Porta Subject: [PATCH 08/12] bcm2835-dma: Need to keep PROT bits set in CS on 40bit controller Date: Sun, 4 Feb 2024 07:59:36 +0100 Message-ID: <98d536c4d9789e176ab83ab3d2257c08f0075bdb.1706948717.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: smtp-out1.suse.de; none X-Spamd-Result: default: False [1.30 / 50.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; R_MISSING_CHARSET(2.50)[]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; REPLY(-4.00)[]; BROKEN_CONTENT_TYPE(1.50)[]; R_RATELIMIT(0.00)[to_ip_from(RLecjp584x17qehbj331hhfqn7)]; RCVD_COUNT_THREE(0.00)[3]; RCPT_COUNT_TWELVE(0.00)[13]; MID_CONTAINS_FROM(1.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email]; FORGED_SENDER(0.30)[andrea.porta@suse.com,aporta@suse.de]; FUZZY_BLOCKED(0.00)[rspamd.com]; MIME_TRACE(0.00)[0:+]; FREEMAIL_CC(0.00)[cerno.tech,gmail.com,raspberrypi.com,suse.com]; FROM_NEQ_ENVFROM(0.10)[andrea.porta@suse.com,aporta@suse.de]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: * X-Spam-Score: 1.30 X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" From: Dom Cobley Resetting them to zero puts DMA channel into secure mode which makes further accesses impossible Cc: Dom Cobley Signed-off-by: Andrea della Porta --- drivers/dma/bcm2835-dma.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index a20700a400a2..1b3f470274b2 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -239,6 +239,8 @@ struct bcm2835_desc { #define BCM2711_DMA40_WR_PAUSED BIT(5) /* Writing is paused */ #define BCM2711_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow contro= l */ #define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write= */ +// we always want to run in supervisor mode +#define BCM2711_DMA40_PROT (BIT(8) | BIT(9)) #define BCM2711_DMA40_ERR BIT(10) #define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16) #define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) @@ -246,10 +248,10 @@ struct bcm2835_desc { #define BCM2711_DMA40_DISDEBUG BIT(29) #define BCM2711_DMA40_ABORT BIT(30) #define BCM2711_DMA40_HALT BIT(31) -#define BCM2711_DMA40_CS_FLAGS(x) ((x) & (BCM2711_DMA40_QOS(15) | \ - BCM2711_DMA40_PANIC_QOS(15) | \ - BCM2711_DMA40_WAIT_FOR_WRITES | \ - BCM2711_DMA40_DISDEBUG)) +#define BCM2711_DMA40_CS_FLAGS(x) ((x) & (BCM2711_DMA40_QOS(15) | \ + BCM2711_DMA40_PANIC_QOS(15) | \ + BCM2711_DMA40_WAIT_FOR_WRITES | \ + BCM2711_DMA40_DISDEBUG)) =20 /* Transfer information bits */ #define BCM2711_DMA40_INTEN BIT(0) @@ -679,7 +681,7 @@ static void bcm2835_dma_abort(struct bcm2835_chan *c) dev_err(c->vc.chan.device->dev, "failed to halt dma\n"); =20 - writel(0, chan_base + BCM2711_DMA40_CS); + writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS); writel(0, chan_base + BCM2711_DMA40_CB); } else { /* @@ -739,7 +741,7 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan = *c) if (c->is_40bit_channel) { writel(to_bcm2711_cbaddr(d->cb_list[0].paddr), c->chan_base + BCM2711_DMA40_CB); - writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq), + writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAG= S(c->dreq), c->chan_base + BCM2711_DMA40_CS); } else { writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); @@ -772,8 +774,13 @@ static irqreturn_t bcm2835_dma_callback(int irq, void = *data) * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dre= q), - c->chan_base + BCM2835_DMA_CS); + if (c->is_40bit_channel) + writel(BCM2835_DMA_INT | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | + BCM2711_DMA40_CS_FLAGS(c->dreq), + c->chan_base + BCM2711_DMA40_CS); + else + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dr= eq), + c->chan_base + BCM2835_DMA_CS); =20 d =3D c->desc; =20 @@ -1227,14 +1234,14 @@ void bcm2711_dma40_memcpy(dma_addr_t dst, dma_addr_= t src, size_t size) scb->next_cb =3D 0; =20 writel(to_bcm2711_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB); - writel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE, + writel(BCM2711_DMA40_MEMCPY_FLAGS | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_= PROT, memcpy_chan + BCM2711_DMA40_CS); =20 /* Poll for completion */ while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END)) cpu_relax(); =20 - writel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS); + writel(BCM2711_DMA40_END | BCM2711_DMA40_PROT, memcpy_chan + BCM2711_DMA4= 0_CS); =20 spin_unlock_irqrestore(&memcpy_lock, flags); } --=20 2.41.0