From nobody Fri Jan 2 17:28:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05C9ACD68FE for ; Tue, 10 Oct 2023 08:35:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442938AbjJJIfo (ORCPT ); Tue, 10 Oct 2023 04:35:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442898AbjJJIfg (ORCPT ); Tue, 10 Oct 2023 04:35:36 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1450DA4; Tue, 10 Oct 2023 01:35:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696926934; x=1728462934; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m7pCDbhKS6+u2jcznAubfaRxlAgJtSYbB0zCkXhtCcE=; b=keJcEqYFaOJEYzUkdJs8Jft5Ct6gYDwV5Lf18cWLvqtj64Kif8BUg2r2 1dEaf9aaXoipwdTjWVzuXgdfobvcwluduObiJeCQoLSk3p151Kd0C2iMg 6vzMDb+Rh+CBdKeE0F0d6RfRqxJ08xEYm9VFMmGFj2zxcV9MPdrskqYoU 2srdz334BLAsk0fpy1PBsE1A+1OwIfVGqsg8Wr3Is1gaV4/Gbeg0h5eTY Q3NA/BDiabkx5f0HO6/ec9HBbokMe3edoknx9tN4qEi1Vie1f+64QI7hw SLKBWbUSf4IbLRsfWduakHttw1NZtQWtgKyBdiy8mhzx9lBm8/9t9ymJh w==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="363689792" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="363689792" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 01:35:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="1084687182" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="1084687182" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 01:35:33 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Michael Roth , Paolo Bonzini , Sean Christopherson , linux-coco@lists.linux.dev, Chao Peng Subject: [PATCH 03/12] x86/mce/inject: Add notrigger entry to suppress MCE injection Date: Tue, 10 Oct 2023 01:35:11 -0700 Message-Id: <97809b68e427922948044e33599c2fc7c9f6134c.1696926843.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata The current x86 MCE injection framework injects MCE when writing to /sys/kernel/debug/mce-inject/bank. KVM wants to inject machine check on behalf of vcpu context instead of the context of writing to the bank file. Because ACPI APEI has a similar requirement and it adds /sys/kernel/debug/apei/notrigger to suppress immediate injection. By Following it, add /sys/kernel/debug/mce-inject/notrigger to suppress MCE injection. The alternative is add new value "notrigger" to /sys/kernel/debug/mce-inject/flags in addition to "sw", "hw", "df", and "th". Because it may break user space ABI, this option follow ACPI APEI error injection. Supposed usage flow: $ echo 1 > notrigger ... setup MCE values $ echo 0 > bank The last step to setup mce value to inject with MC bank 0. Originally this step injects mce. With noijnect=3D1, don't inject. $ echo 1 > /sys/kernel/debug/kvm/-/vcpu/mce-inject tell KVM to inject MCE in the context of vcpu. Signed-off-by: Isaku Yamahata --- arch/x86/kernel/cpu/mce/inject.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 461858ae18f9..88603a6c0afe 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -34,6 +34,7 @@ #include "internal.h" =20 static bool hw_injection_possible; +static u64 notrigger; =20 /* * Collect all the MCi_XXX settings @@ -598,6 +599,8 @@ static int inj_bank_set(void *data, u64 val) } =20 m->bank =3D val; + if (notrigger) + return 0; =20 /* * sw-only injection allows to write arbitrary values into the MCA @@ -637,6 +640,21 @@ MCE_INJECT_GET(bank); =20 DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); =20 +static int inj_notrigger_get(void *data, u64 *val) +{ + *val =3D notrigger; + return 0; +} + +static int inj_notrigger_set(void *data, u64 val) +{ + notrigger =3D val; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(notrigger_fops, inj_notrigger_get, inj_notrigger_s= et, + "%llx\n"); + static const char readme_msg[] =3D "Description of the files and their usages:\n" "\n" @@ -685,6 +703,9 @@ static const char readme_msg[] =3D "\n" "mcgstatus:\t Set MCG_STATUS: the bits in that MSR describes the current s= tate\n" "\t of the processor after the MCE.\n" +"\n" +"notrigger:\t Suppress triggering the injection when set to non-zero\n" +"\t The injection is triggered by other way.\n" "\n"; =20 static ssize_t @@ -714,6 +735,8 @@ static struct dfs_node { { .name =3D "cpu", .fops =3D &extcpu_fops, .perm =3D S_IRUSR | S_IWUSR }, { .name =3D "mcgstatus", .fops =3D &mcgstatus_fops, .perm =3D S_IRUSR | S_IWUSR }, + { .name =3D "notrigger", .fops =3D ¬rigger_fops, + .perm =3D S_IRUSR | S_IWUSR }, { .name =3D "README", .fops =3D &readme_fops, .perm =3D S_IRUSR | S_IRGRP= | S_IROTH }, }; =20 --=20 2.25.1