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charset="utf-8" Several resctrl MSRs in the AMD address range (0xc0000xxx) were defined with an MSR_IA32_ prefix even though they are AMD-specific and unrelated to Intel's IA32 resctrl MSRs. The MSR_IA32_ prefix is misleading when reading or grepping the codebase alongside the Intel MSR_IA32_* resctrl definitions in msr-index.h. Rename the AMD resctrl MSR definitions, update all call sites, and keep the tools copy of msr-index.h in sync: MSR_IA32_MBA_BW_BASE -> MSR_AMD_MBA_BW_BASE MSR_IA32_SMBA_BW_BASE -> MSR_AMD_SMBA_BW_BASE MSR_IA32_L3_QOS_ABMC_CFG -> MSR_AMD_L3_QOS_ABMC_CFG MSR_IA32_L3_QOS_EXT_CFG -> MSR_AMD_L3_QOS_EXT_CFG MSR_IA32_EVT_CFG_BASE -> MSR_AMD_EVT_CFG_BASE No functional changes. Suggested-by: Borislav Petkov (AMD) Signed-off-by: Babu Moger --- arch/x86/include/asm/msr-index.h | 10 +++++----- arch/x86/kernel/cpu/resctrl/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 6 +++--- arch/x86/kernel/cpu/resctrl/internal.h | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 6 +++--- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- fs/resctrl/rdtgroup.c | 4 ++-- tools/arch/x86/include/asm/msr-index.h | 10 +++++----- 8 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 18c4be75e927..b68ad3088779 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1290,11 +1290,11 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 =20 /* - AMD: */ -#define MSR_IA32_MBA_BW_BASE 0xc0000200 -#define MSR_IA32_SMBA_BW_BASE 0xc0000280 -#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd -#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff -#define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_AMD_MBA_BW_BASE 0xc0000200 +#define MSR_AMD_SMBA_BW_BASE 0xc0000280 +#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd +#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_AMD_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index cf780c1969e9..cd32851876e2 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1051,10 +1051,10 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_per_cpu_cfg =3D true; r->cache.min_cbm_bits =3D 0; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { - hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; + hw_res->msr_base =3D MSR_AMD_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; } else if (r->rid =3D=3D RDT_RESOURCE_SMBA) { - hw_res->msr_base =3D MSR_IA32_SMBA_BW_BASE; + hw_res->msr_base =3D MSR_AMD_SMBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index e74f1ed54b86..ed14256d7f3b 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -102,9 +102,9 @@ static void resctrl_sdciae_set_one_amd(void *arg) bool *enable =3D arg; =20 if (*enable) - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); else - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); } =20 static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) @@ -114,7 +114,7 @@ static void _resctrl_sdciae_enable(struct rdt_resource = *r, bool enable) /* Walking r->ctrl_domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); =20 - /* Update MSR_IA32_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ + /* Update MSR_AMD_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ list_for_each_entry_rcu(d, &r->ctrl_domains, hdr.list, lockdep_is_cpus_he= ld()) on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index e3cfa0c10e92..6e7f6e0d1bf8 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -49,7 +49,7 @@ struct arch_mbm_state { #define ABMC_EXTENDED_EVT_ID BIT(31) #define ABMC_EVT_ID BIT(0) =20 -/* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */ +/* Setting bit 1 in MSR_AMD_L3_QOS_EXT_CFG enables the SDCIAE feature. */ #define SDCIAE_ENABLE_BIT 1 =20 /** @@ -187,7 +187,7 @@ union cpuid_0x10_x_edx { }; =20 /* - * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG. + * ABMC counters are configured by writing to MSR_AMD_L3_QOS_ABMC_CFG. * * @bw_type : Event configuration that represents the memory * transactions being tracked by the @cntr_id. diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 3838e0a13d36..a2c9acc7aec8 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -498,9 +498,9 @@ static void resctrl_abmc_set_one_amd(void *arg) bool *enable =3D arg; =20 if (*enable) - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); else - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); } =20 /* @@ -542,7 +542,7 @@ static void resctrl_abmc_config_one_amd(void *info) { union l3_qos_abmc_cfg *abmc_cfg =3D info; =20 - wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full); + wrmsrq(MSR_AMD_L3_QOS_ABMC_CFG, abmc_cfg->full); } =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 5ffa39fa86fa..6590ebf6b29d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -96,7 +96,7 @@ void resctrl_arch_mon_event_config_read(void *_config_inf= o) pr_warn_once("Invalid event id %d\n", config_info->evtid); return; } - rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval); + rdmsrq(MSR_AMD_EVT_CFG_BASE + index, msrval); =20 /* Report only the valid event configuration bits */ config_info->mon_config =3D msrval & MAX_EVT_CONFIG_BITS; @@ -112,7 +112,7 @@ void resctrl_arch_mon_event_config_write(void *_config_= info) pr_warn_once("Invalid event id %d\n", config_info->evtid); return; } - wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config); + wrmsrq(MSR_AMD_EVT_CFG_BASE + index, config_info->mon_config); } =20 static void l3_qos_cfg_update(void *arg) diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 30df902ea776..30c4c57e0e4c 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1785,8 +1785,8 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, mon_info.mon_config =3D val; =20 /* - * Update MSR_IA32_EVT_CFG_BASE MSR on one of the CPUs in the - * domain. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE + * Update MSR_AMD_EVT_CFG_BASE MSR on one of the CPUs in the + * domain. The MSRs offset from MSR_AMD_EVT_CFG_BASE * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index eff29645719b..5f11fa3b7b1b 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -1279,11 +1279,11 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 =20 /* - AMD: */ -#define MSR_IA32_MBA_BW_BASE 0xc0000200 -#define MSR_IA32_SMBA_BW_BASE 0xc0000280 -#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd -#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff -#define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_AMD_MBA_BW_BASE 0xc0000200 +#define MSR_AMD_SMBA_BW_BASE 0xc0000280 +#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd +#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_AMD_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 --=20 2.43.0