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[188.123.113.247]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca4c2sm32598535e9.36.2024.07.04.10.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 10:42:20 -0700 (PDT) Date: Thu, 4 Jul 2024 19:42:18 +0200 From: Stanislav Jakubek To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Baolin Wang , Chunyan Zhang Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: sprd: reorder clock-names after clocks Message-ID: <9623744b096c026f481fc5d03ba8f1643e487534.1720112081.git.stano.jakubek@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DT convention is to have property-names after property. While at it, cleanup indentation for some clocks. No functional change. Signed-off-by: Stanislav Jakubek --- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 4 +-- arch/arm64/boot/dts/sprd/ums512.dtsi | 4 +-- arch/arm64/boot/dts/sprd/whale2.dtsi | 38 +++++++++++++++------------ 3 files changed, 25 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sp= rd/sc9863a.dtsi index a7b897966882..e5a2857721e2 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -556,9 +556,9 @@ sdio0: mmc@20300000 { reg =3D <0 0x20300000 0 0x1000>; interrupts =3D ; =20 - clock-names =3D "sdio", "enable"; clocks =3D <&aon_clk CLK_SDIO0_2X>, <&apahb_gate CLK_SDIO0_EB>; + clock-names =3D "sdio", "enable"; assigned-clocks =3D <&aon_clk CLK_SDIO0_2X>; assigned-clock-parents =3D <&rpll CLK_RPLL_390M>; =20 @@ -572,9 +572,9 @@ sdio3: mmc@20600000 { reg =3D <0 0x20600000 0 0x1000>; interrupts =3D ; =20 - clock-names =3D "sdio", "enable"; clocks =3D <&aon_clk CLK_EMMC_2X>, <&apahb_gate CLK_EMMC_EB>; + clock-names =3D "sdio", "enable"; assigned-clocks =3D <&aon_clk CLK_EMMC_2X>; assigned-clock-parents =3D <&rpll CLK_RPLL_390M>; =20 diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/spr= d/ums512.dtsi index 4c080df48724..efa14309cc4e 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -849,9 +849,9 @@ sdio0: mmc@1100000 { compatible =3D "sprd,sdhci-r11"; reg =3D <0x1100000 0x1000>; interrupts =3D ; - clock-names =3D "sdio", "enable"; clocks =3D <&ap_clk CLK_SDIO0_2X>, <&apapb_gate CLK_SDIO0_EB>; + clock-names =3D "sdio", "enable"; assigned-clocks =3D <&ap_clk CLK_SDIO0_2X>; assigned-clock-parents =3D <&pll1 CLK_RPLL>; status =3D "disabled"; @@ -861,9 +861,9 @@ sdio3: mmc@1400000 { compatible =3D "sprd,sdhci-r11"; reg =3D <0x1400000 0x1000>; interrupts =3D ; - clock-names =3D "sdio", "enable"; clocks =3D <&ap_clk CLK_EMMC_2X>, <&apapb_gate CLK_EMMC_EB>; + clock-names =3D "sdio", "enable"; assigned-clocks =3D <&ap_clk CLK_EMMC_2X>; assigned-clock-parents =3D <&pll1 CLK_RPLL>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/spr= d/whale2.dtsi index cdf52fd78ee4..a28f995fb3ff 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -75,9 +75,10 @@ uart0: serial@0 { "sprd,sc9836-uart"; reg =3D <0x0 0x100>; interrupts =3D ; - clock-names =3D "enable", "uart", "source"; clocks =3D <&apapb_gate CLK_UART0_EB>, - <&ap_clk CLK_UART0>, <&ext_26m>; + <&ap_clk CLK_UART0>, + <&ext_26m>; + clock-names =3D "enable", "uart", "source"; status =3D "disabled"; }; =20 @@ -86,9 +87,10 @@ uart1: serial@100000 { "sprd,sc9836-uart"; reg =3D <0x100000 0x100>; interrupts =3D ; - clock-names =3D "enable", "uart", "source"; clocks =3D <&apapb_gate CLK_UART1_EB>, - <&ap_clk CLK_UART1>, <&ext_26m>; + <&ap_clk CLK_UART1>, + <&ext_26m>; + clock-names =3D "enable", "uart", "source"; status =3D "disabled"; }; =20 @@ -97,9 +99,10 @@ uart2: serial@200000 { "sprd,sc9836-uart"; reg =3D <0x200000 0x100>; interrupts =3D ; - clock-names =3D "enable", "uart", "source"; clocks =3D <&apapb_gate CLK_UART2_EB>, - <&ap_clk CLK_UART2>, <&ext_26m>; + <&ap_clk CLK_UART2>, + <&ext_26m>; + clock-names =3D "enable", "uart", "source"; status =3D "disabled"; }; =20 @@ -108,9 +111,10 @@ uart3: serial@300000 { "sprd,sc9836-uart"; reg =3D <0x300000 0x100>; interrupts =3D ; - clock-names =3D "enable", "uart", "source"; clocks =3D <&apapb_gate CLK_UART3_EB>, - <&ap_clk CLK_UART3>, <&ext_26m>; + <&ap_clk CLK_UART3>, + <&ext_26m>; + clock-names =3D "enable", "uart", "source"; status =3D "disabled"; }; }; @@ -129,8 +133,8 @@ ap_dma: dma-controller@20100000 { /* For backwards compatibility: */ #dma-channels =3D <32>; dma-channels =3D <32>; - clock-names =3D "enable"; clocks =3D <&apahb_gate CLK_DMA_EB>; + clock-names =3D "enable"; }; =20 sdio3: mmc@50430000 { @@ -138,10 +142,10 @@ sdio3: mmc@50430000 { reg =3D <0 0x50430000 0 0x1000>; interrupts =3D ; =20 - clock-names =3D "sdio", "enable", "2x_enable"; clocks =3D <&aon_prediv CLK_EMMC_2X>, - <&apahb_gate CLK_EMMC_EB>, - <&aon_gate CLK_EMMC_2X_EN>; + <&apahb_gate CLK_EMMC_EB>, + <&aon_gate CLK_EMMC_2X_EN>; + clock-names =3D "sdio", "enable", "2x_enable"; assigned-clocks =3D <&aon_prediv CLK_EMMC_2X>; assigned-clock-parents =3D <&clk_l0_409m6>; =20 @@ -194,8 +198,8 @@ hwlock: hwspinlock@40500000 { compatible =3D "sprd,hwspinlock-r3p0"; reg =3D <0 0x40500000 0 0x1000>; #hwlock-cells =3D <1>; - clock-names =3D "enable"; clocks =3D <&aon_gate CLK_SPLK_EB>; + clock-names =3D "enable"; }; =20 eic_debounce: gpio@40210000 { @@ -258,9 +262,9 @@ watchdog@40310000 { reg =3D <0 0x40310000 0 0x1000>; interrupts =3D ; timeout-sec =3D <12>; - clock-names =3D "enable", "rtc_enable"; clocks =3D <&aon_gate CLK_APCPU_WDG_EB>, - <&aon_gate CLK_AP_WDG_RTC_EB>; + <&aon_gate CLK_AP_WDG_RTC_EB>; + clock-names =3D "enable", "rtc_enable"; }; }; =20 @@ -277,9 +281,9 @@ agcp_dma: dma-controller@41580000 { /* For backwards compatibility: */ #dma-channels =3D <32>; dma-channels =3D <32>; - clock-names =3D "enable", "ashb_eb"; clocks =3D <&agcp_gate CLK_AGCP_DMAAP_EB>, - <&agcp_gate CLK_AGCP_AP_ASHB_EB>; + <&agcp_gate CLK_AGCP_AP_ASHB_EB>; + clock-names =3D "enable", "ashb_eb"; }; }; }; --=20 2.34.1