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Thu, 15 Jan 2026 10:23:38 -0800 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH rc v7 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Date: Thu, 15 Jan 2026 10:23:31 -0800 Message-ID: <95f813482d7acf6de45e85c9e0caa3bec52a6a65.1768501336.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|CY8PR12MB7660:EE_ X-MS-Office365-Filtering-Correlation-Id: 97709389-c673-4902-6654-08de54633eda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6Zcl0kDEsYBlVTOZQIbCJwcY3nL4i8bvydc5uDTrZUekn40N+iX2GyevBTvU?= =?us-ascii?Q?pJIspiEQnGxG9CybgT4Ais9TvtZmxGieuEgoMBIxQivhrb3Fvb9HJwuHE4Jv?= =?us-ascii?Q?g/t2JxoIxfJt4nu4/8W6cfTkLAMU6MntliyQc8YUuQGHRtrMqInawcM8OEJC?= =?us-ascii?Q?WmQvxspYyfY/SpV8s6/s3RxtOnAMNltJinSxzLVpUTDCh0cIMbiv6T1p0TXt?= =?us-ascii?Q?OZfquBprtsE6STC1kjg31GwrKP25kiZh7cH9FYEjGpKtHJ2GgyOEgk86QPNm?= =?us-ascii?Q?aigTvtaIyNiYg44+C5pdXD/nb45EuiBWtjjgcXlYhcnNMIy/P1TRu5dCs/OH?= =?us-ascii?Q?xas2HPAX+fz66zLffgNXRZm0fzD5k1azNaGRIevvrsmaD+4IfpdVuj9z2xe2?= =?us-ascii?Q?TxyeocIkKXXgUFRKbseBD7hzjlAQ6+xVJk7+7omF3t1v+Kr9/5KJrmtRVfw4?= =?us-ascii?Q?CXdJGAjxQN/HJehknt49KgujPsb9S7sLjeSMsI/lIVJzTDKCUi3dOEo2/+We?= =?us-ascii?Q?0yUuPh01NlWJGOGSxlBTsXzsp6nqt2wCihZYdZMX0z6Gh1H08se1Imd32yDc?= =?us-ascii?Q?NcZ3CgyWKsFx5v4qsooHYeYk/Td5kwGgnbmK4WZ4YPykPZSM9hEd0GEwWapb?= =?us-ascii?Q?NJdCBl19X5QInwfaUUdVW5AeekGs9baQJybOgTWt5wTAzkliAZcOTQsprZhy?= =?us-ascii?Q?ue/Vg9Vw+5LfvQYvzqefz09vMkexhzeiFv2pjaOAuiDyc12hTjVKzm3EQ2MG?= =?us-ascii?Q?vQLLPa++7BSOEYvcSeMPgsmGaEcnkxIdwn29W0XHvj84BylC1wnm63hnpYzE?= =?us-ascii?Q?e5ZXFmoqkSv3uyXe7kLYVYJO1DszvC+2glMSWtyY7xQNpKOTraLOt9AuugtL?= =?us-ascii?Q?6T2Y3M18xLIbVVFblAjuBwDfq+5yjLrFrM4slTxZ7WC9g1dt2W4njQi5dHoP?= =?us-ascii?Q?PIQyttfZDzRnWhZBnTH+EpxUtSVVnepA+bbcUBW6gj2O3UkpQ+/6XT0mdzAs?= =?us-ascii?Q?kLvawMWYZqUbqyZfU9SUinPJVq2eFTvG+ZMHJcwTvfE8Ykdp7VzTQfWR8BwA?= =?us-ascii?Q?/UiLzZ1NSs8vCv8qq0hOSnddT9tfwLQ9gTC5+IbubQw1ZAs6USDzlREJfB+B?= =?us-ascii?Q?nK3RedLuL2syB5UidO/QBe4oN0hAoP3eYEiyr2MS5/5/Kf9hnq5yn+vKukRg?= =?us-ascii?Q?BbLkNOJjs5JSeoJrro1O79xFGx9jvcCX6ZnnbuputY3Un9Q4ds6Yr37Niw6t?= =?us-ascii?Q?ue0VQBrtCkhb3hxIcz203LAC31LrZHqiuGAqBIytiztidgBztsGdejcczQ/E?= =?us-ascii?Q?uKHS911H1C1NJkKNkFBv2MAYHAei+isNZlI5+B8TEkabRpjMsxJi0s8LTpxu?= =?us-ascii?Q?vU3MSHM8q+XpKqOJI9HvoqJBfGvm24HQZpAQRhLIeXUEl0E1EHa8134r+6dx?= =?us-ascii?Q?bgMdasRS9bYp2VypqpnPLkXOev4/Do2gA05aALDl5627NCl4qUBTWi/k7l+O?= =?us-ascii?Q?AdWlWtz+hhatEQuqkRIBJurhW8FXgG+Xm4ZR6aEOFHqQpMaNnMjFGzHTsW/W?= =?us-ascii?Q?IVRZX5C/Ti3W4lr65K0vp4qNuZw5u4ukF2o1Xm7NWBO+5QkTTT967KyGVLKH?= =?us-ascii?Q?R+OYqH4Ff44l15z7W7wm8M/bf6kCSEvgzsuvo9O07pCHwA9mDcMULpFE6ITf?= =?us-ascii?Q?m4wq3Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2026 18:23:56.5912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97709389-c673-4902-6654-08de54633eda X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7660 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Reviewed-by: Shuai Xue Reviewed-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index b254a94b2003..69c9ef441fc1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -33,8 +33,12 @@ static struct mm_struct sva_mm =3D { enum arm_smmu_test_master_feat { ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), + ARM_SMMU_MASTER_TEST_NESTED =3D BIT(2), }; =20 +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, + enum arm_smmu_test_master_feat feat); + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -210,6 +214,18 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_= smmu_ste *ste, }; =20 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { + struct arm_smmu_ste s2ste; + int i; + + arm_smmu_test_make_s2_ste(&s2ste, + feat & ~ARM_SMMU_MASTER_TEST_NESTED); + ste->data[0] |=3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + for (i =3D 2; i < NUM_ENTRY_QWORDS; i++) + ste->data[i] =3D s2ste.data[i]; + } } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -567,6 +583,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + /* Expect an additional sync to unset ignored bits: EATS and MEV */ + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -613,6 +658,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0